Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Device power-on enable conditions:
If none of the device power-on disable conditions is met, the following conditions are available to turn
on and/or maintain the ON state of the device:
• PWRON signal low level.
• Or PWRHOLD signal high level.
• Or DEV_ON control bit set to 1 (default inactive).
• Or interrupt flag active (default INT1 low) while the device is off (NRESPWRON = 0) generates a
power-on enable condition during a fixed delay (T
DOINT1
pulse duration defined in Section 5.22.2,
Power Control Timing).
The power-on enable condition pulse occurs only if the interrupt status bit is initially low (no
previous identical interrupt pending in the status register).
The Interrupt sources expected when the device is off are:
• PWRON low-level interrupt (PWRON_IT = 1 in INT_STS_REG register)
• PWRHOLD rising-edge interrupt (PWRHOLD_IT = 1 in INT_STS_REG register)
The Interrupt sources expected if enabled when the device is off are:
• RTC Alarm interrupt (RTC_ALARM_IT = 1 or RTC_PERIOD_IT = 1 in INT_STS_REG register)
• First-time input voltage rising above VMBHI threshold (Boot mode or EEPROM dependent) and
input voltage > VMBCH threshold (VMBCH_IT = 1 in INT_STS_REG register).
GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its
associated interrupt is not masked, but can be used as an interrupt source to wake up the device from
SLEEP-to-ACTIVE state.
Device power-on disable conditions:
• PWRON signal low level during more than the long-press delay: t
dPWRONLP
(can be disabled though
register programming). The interrupt corresponding to this condition is PWRON_LP_IT in the
INT_STS_REG register.
• Or Die temperature has reached the thermal shutdown threshold.
• Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is
in OFF state).
Device SLEEP enable conditions:
• SLEEP signal low level (default, or high level depending on the programmed polarity)
• And DEV_SLP control bit set to 1
• And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending
The SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal in the
active polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 once,
after device turn-on.
Copyright © 2010–2014, Texas Instruments Incorporated Detailed Description 47
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109