Datasheet

SWCS046-024
SLEEP
t
ACT2SLP
VIO/VFBIO 1.8 V
PWM mode
VAUX1
VDD2/VFB2
VDD1/VFB1
VPLL
VDAC
VAUX2
VMMC
CLK32KOUT
SWIO
SW2
SW1
1.8 V
Low-power mode
1.8 V
PWM mode
1.8 V
Active mode
1.8 V
Low-power mode
1.8 V
Active mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
3.3 V
1.2 V
PWM mode
Off
1.8 V
Active mode
1.8 V
Active mode
1.8 V
Active mode
3.3 V
Active mode
3.3 V
Low-power mode
Off
Off
1.8 V
Active mode
1.8 V
Active mode
3.3 V
Active mode
1.2 V
PWM mode
1.8 V
Active mode
1.8 V
Active mode
t
SLP2ACT
t
SLP2ACTCK32K
t
dSLPON1
t
dSLPONST
t
dSLPONST
t
dONDCDCSLP
t
ACT2SLPCK32K
Pulse skip mode
TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
5.22.2.3 Device SLEEP State Control
Figure 5-6 shows the device SLEEP state control timing characteristics.
NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1,
VPLL_SETOFF = 1, VAUX2_KEEPON = 1
Figure 5-6. Device SLEEP State Control
Table 5-6. Device SLEEP State Control Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SLEEP falling edge to supply in low power
2 × t
CK32k
= 3 × t
CK32k
=
t
ACT2SLP
mode µs
62 94
(SLEEP resynchronization delay)
t
ACT2SLP
+ 3 ×
t
ACT2SLP
SLEEP falling edge to CLK32KOUT low 156 188 µs
t
CK32k
SLEEP rising edge to supply in high power 8 × t
CK32k
= 9 × t
CK32k
=
t
SLP2ACT
µs
mode 250 281
t
SLP2ACT
+ 3 ×
t
SLP2ACTCK32K
SLEEP rising edge to CLK32KOUT running 344 375 µs
t
CK32k
SLEEP rising edge to time step 1 of the tun-on t
SLP2ACT
+ 1 ×
t
dSLPON1
281 312 µs
sequence from SLEEP state t
CK32k
turn-on sequence step duration, from SLEEP
state
TSLOT_LENGTH[1:0] = 00 0
t
dSLPONST
µs
TSLOT_LENGTH[1:0] = 01 200
TSLOT_LENGTH[1:0] = 10 500
TSLOT_LENGTH[1:0] = 11 2000
VDD1, VDD2 or VIO tun-on delay from tun-on 2 × t
CK32k
=
t
dSLPONDCDC
us
sequence time step 62
42 Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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