Datasheet

PWRON
VIO
INT1
NRESPWRON
PWRHOLD
PWRON_LP_IT=1
PWRON_IT=1
Switch-off
sequence
t
dPWRONLPTO
t
dPWRONLP
t
dbPWRONF
SWCS046-010
PWRON_IT=1
TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
Figure 5-5 shows the long-press turn-off timing characteristics.
NOTE: If the DEV_ON control bit is set to 1 or PWRHOLD is kept high, the device will be turned on again after PWRON long
press turn-off and PWRON released.
Figure 5-5. PWRON Long-Press Turn-Off
Table 5-5 lists the power control timing characteristics.
Table 5-5. Power Control Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BOOT[1:0] = 00, RC oscillator 0.1
BOOT[1:0] = 01, Quartz
t
d32KON
: 32-kHz Oscillator turn-on time 400 2000 ms
oscillator
BOOT[1:0] = 01, Bypass clock 0.1
3 ×
4 × t
CK32k
t
dbVMBHI
: VMBHI rising-edge debouncing delay t
CK32k
= µs
= 125
94
3 ×
t
dbVMBDCH
: Main Battery voltage = VMBDCH threshold to INT1 4 × t
CK32k
t
CK32k
= s
falling-edge delay = 125
94
3 ×
t
dbVMBLO
: Main Battery voltage = VMBLO threshold to 4 × t
CK32k
t
CK32k
= s
NRESPWRON falling-edge delay = 125
94
t
dbPWRONF
: PWRON falling-edge debouncing delay 500 550 ms
3 ×
4 × t
CK32k
t
dbPWRONR
: PWRON rising-edge debouncing delay t
CK32k
= µs
= 125
94
2 × 3 ×
t
dbPWRHOLD
: PWRON rising-edge debouncing delay t
CK32k
= t
CK32k
= µs
63 94
t
dOINT
: INT1 (internal) Power-on pulse duration after PWRON
1 s
low-level (debounced) event
t
dONPWHOLD
: delay to set high PWRHOLD signal or DEV_ON
984 ms
control bit after NRESPWRON released to keep on the supplies
PWRON falling edge to
t
dPWRONLP
: PWRON long-press delay to interrupt 6 s
PWON_LP_IT = 1
PWRON falling edge to
t
dPWRONLPTO
: PWRON long-press delay to turn-off 8 s
NRESPWRON falling edge
Copyright © 2010–2014, Texas Instruments Incorporated Specifications 41
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