Datasheet

TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046U –MARCH 2010–REVISED JUNE 2014
5.22 Timing and Switching Characteristics
5.22.1 Switch-On/-Off Sequences and Timing
Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or
through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.
5.22.1.1 BOOT1 = 0, BOOT0 = 0
Table 5-1 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this
boot mode is provided in Figure 5-1.
Table 5-1. Fixed Boot Mode: 00
TPS65910
Register Bit Description
Boot 00
VDD1_OP_REG SEL VDD1 voltage level selection for boot 1.2 V
VDD1_REG VGAIN_SEL VDD1 gain selection, x1 or x2 x1
EEPROM VDD1 time slot selection 3
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable skip enabled
VDD2_OP_REG/VDD2_SR_REG SEL VDD2 voltage level selection for boot 1.1 V
VDD2_REG VGAIN_SEL VDD2 Gain selection, x1 or x3 x3
EEPROM VDD2 time slot selection 2
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable skip enabled
VIO_REG SEL VIO voltage selection 1.8 V
EEPROM VIO time slot selection 1
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable skip enabled
EEPROM VDD3 time slot OFF
VDIG1_REG SEL LDO voltage selection 1.2 V
EEPROM LDO time slot OFF
VDIG2_REG SEL LDO voltage selection 1.0 V
EEPROM LDO time slot OFF
VDAC_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 5
VPLL_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 4
VAUX1_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 1
VMMC_REG SEL LDO voltage selection 3.3 V
EEPROM LDO time slot 6
VAUX33_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot OFF
VAUX2_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 5
CLK32KOUT pin CLK32KOUT time slot 7
NRESPWRON pin NRESPWRON time slot 7 + 1
0: VRTC LDO will be in low-power mode during OFF state
VRTC_OFFMAS
VRTC_REG Low-power mode
K
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
DEVCTRL_REG RTC_PWDN 1
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
DEVCTRL_REG CK32K_CTRL RC
1: Clock source is internal RC oscillator
Copyright © 2010–2014, Texas Instruments Incorporated Specifications 35
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