Datasheet

VFB1
INT1
PWRON
VREF
REFGND
Test interface
CLK32KOUT
VAUX33
VMMC
OSC32KIN
OSC32KOUT
TESTV
SLEEP
NRESPWRON
PWRHOLD
BOOT1
BOOT0
SDASR_EN2
SCLSR_EN1
SDA_SDI
VDAC
VPLL
VAUX1
VRTC
Real-time
clock
VFB3
SW3
VDIG2
VAUX2
VDIG1
VDD1
(SMPS)
VCC1
GND1
SW1
VFBIO
VBAT
VCC7
VCC7
VCC7
VBAT
VBAT
VBAT
VCC6
VCC3
VCC4
VCC5
VCC 7
VBAT
VCC7
VDDIO
VDDIO
AGND2
AGND
AGND
GNDA
GNDA
DGND
VAUX33
REFGND
GND3
OSC
32-kHz
SCL_SCK
Bus
control
GPIO_CKSYNC
Power
control
state-
machine
Analog
references
and comparators
VBACKUP
Backup
management
VRTC (LDO)
and POR
VFB2
VCC2
GND2
SW2
VCCIO
GNDIO
SWIO
GNDP
AGND
AGND2
AGND2
VDAC
(LDO)
VPLL
(LDO)
VAUX1
(LDO)
VAUX2
(LDO)
VDIG1
(LDO)
AGND2
AGND2
AGND2
VDIG2
(LDO)
VAUX33
(LDO)
VMMC
(LDO)
I C
2
I C
2
AGND2
AGND
AGND
VCC7
VCC7
VCC4
VDD2
(SMPS)
VIO
(SMPS)
VDD3
(SMPS)
SWCS046-001
GNDP: Power pad ground
Ci
(VCC7)
Co
(VRTC)
Co
(VREF)
Co
(VDAC)
Ci
(VCC5)
C
BB
Co
(VPLL)
Co
(VAUX1)
Ci
(VCC4)
Co
(VAUX2)
DGND AGND AGND2
GND3
Co
(VMMC)
VBAT
Ci
(VCC4)
Co
(VAUX33)
Co
(VDIG2)
Co
(VDIG1)
Co
(VIO)
Ci
(VCCIO)
VBAT
Ci
(VCC2)
Co
(VDD2)
VBAT
Ci
(VCC1)
Co
(VDD1)
Co
(VDD3)
Ci
(VDD3)
TPS65910 , TPS65910A , TPS65910A3 , TPS659101
TPS659102 , TPS659103 , TPS659104 , TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014 www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the top-level diagram of the device.
Figure 1-1. 48-QFN Top-Level Diagram
2 Device Overview Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109