Datasheet
TPS65910
,
TPS65910A
,
TPS65910A3
,
TPS659101
TPS659102
,
TPS659103
,
TPS659104
,
TPS659105
TPS659106, TPS659107, TPS659108, TPS659109
SWCS046U –MARCH 2010–REVISED JUNE 2014
www.ti.com
5.22.1.2 BOOT1 = 0, BOOT0 = 1
Table 5-3 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this
boot mode is provided in Figure 5-2.
Table 5-3. Fixed Boot Mode: 01
TPS65910
Register Bit Description
Boot 01
VDD1_OP_REG SEL VDD1 voltage level selection for boot 1.2 V
VDD1_REG VGAIN_SEL VDD1 Gain selection, x1 or x2 x1
EEPROM VDD1 time slot selection 3
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable Skip enabled
VDD2_OP_REG/VDD2_SR_REG SEL VDD2 voltage level selection for boot 1.2 V
VDD2_REG VGAIN_SEL VDD2 Gain selection, x1 or x3 x1
EEPROM VDD2 time slot selection 4
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable Skip enabled
VIO_REG SEL VIO voltage selection 1.8 V
EEPROM VIO time slot selection 1
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable Skip enabled
EEPROM VDD3 time slot OFF
VDIG1_REG SEL LDO voltage selection 1.2 V
EEPROM LDO time slot OFF
VDIG2_REG SEL LDO voltage selection 1.0 V
EEPROM LDO time slot OFF
VDAC_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot OFF
VPLL_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 2
VAUX1_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot OFF
VMMC_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot OFF
VAUX33_REG SEL LDO voltage selection 3.3 V
EEPROM LDO time slot 6
VAUX2_REG SEL LDO voltage selection 1.8 V
EEPROM LDO time slot 5
CLK32KOUT pin CLK32KOUT time slot 7
NRESPWRON pin NRESPWRON time slot 7+1
0: VRTC LDO will be in low-power mode during OFF state
VRTC_OFFMAS
VRTC_REG low-power mode
K
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
DEVCTRL_REG RTC_PWDN 1
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
DEVCTRL_REG CK32K_CTRL Crystal
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
TSLOT_LENGTH
DEVCTRL2_REG 0: 0.5 ms 2 ms
[0]
1: 2 ms
0: INT1 signal will be active-low
DEVCTRL2_REG IT_POL Active-low
1: INT1 signal will be active-high
38 Specifications Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109