Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013 www.ti.com
Table 74. INT_STS_REG
Address Offset 0x50
Physical Address Instance
Description Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type RW
7 6 5 4 3 2 1 0
HOTDIE_IT PWRHOLD_IT PWRON_LP_IT PWRON_IT VMBHI_IT VMBDCH_IT
RTC_ALARM_IT
RTC_PERIOD_IT
Bits Field Name Description Type Reset
7 RTC_PERIOD_IT RTC period event interrupt status. RW 0
W1 to Clr
6 RTC_ALARM_IT RTC alarm event interrupt status. RW 0
W1 to Clr
5 HOTDIE_IT Hot die event interrupt status. RW 0
W1 to Clr
4 PWRHOLD_IT PWRHOLD event interrupt status. RW 0
W1 to Clr
3 PWRON_LP_IT PWRON Long Press event interrupt status. RW 0
W1 to Clr
2 PWRON_IT PWRON event interrupt status. RW 0
W1 to Clr
1 VMBHI_IT VBAT > VMBHI event interrupt status RW 0
W1 to Clr
0 VMBDCH_IT VBAT > VMBDCH event interrupt status. RW 0
Active only if Main Battery comparator VMBCH programmable threshold W1 to Clr
is not bypassed (VMBCH_SEL[1:0] ≠ 00)
Table 75. INT_MSK_REG
Address Offset 0x51
Physical Address Instance
Description Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type RW
7 6 5 4 3 2 1 0
VMBHI_IT_MSK
HOTDIE_IT_MSK
PWRON_IT_MSK
VMBDCH_IT_MSK
PWRHOLD_IT_MSK
PWRON_LP_IT_MSK
RTC_ALARM_IT_MSK
RTC_PERIOD_IT_MSK
82 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109