Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013 www.ti.com
Table 70. EN2_LDO_ASS_REG
Address Offset 0x47
Physical Address Instance
Description Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also
defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
VDAC_EN2 VPLL_EN2 VAUX33_EN2 VAUX2_EN2 VAUX1_EN2 VDIG2_EN2 VDIG1_EN2 VMMC_EN2
Bits Field Name Description Type Reset
7 VDAC_EN2 Setting supply state control though SDASR_EN2 signal RW 0
6 VPLL_EN2 Setting supply state control though SDASR_EN2 signal RW 0
5 VAUX33_EN2 Setting supply state control though SDASR_EN2 signal RW 0
4 VAUX2_EN2 Setting supply state control though SDASR_EN2 signal RW 0
3 VAUX1_EN2 Setting supply state control though SDASR_EN2 signal RW 0
2 VDIG2_EN2 Setting supply state control though SDASR_EN2 signal RW 0
1 VDIG1_EN2 Setting supply state control though SDASR_EN2 signal RW 0
0 VMMC_EN2 Setting supply state control though SDASR_EN2 signal RW 0
Table 71. EN2_SMPS_ASS_REG
Address Offset 0x48
Physical Address Instance
Description Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
Type RW
7 6 5 4 3 2 1 0
RSVD SPARE_EN2 VDD3_EN2 VDD2_EN2 VDD1_EN2 VIO_EN2
Bits Field Name Description Type Reset
7:5 RSVD Reserved bit RO 0x0
R returns
0s
4 SPARE_EN2 Spare bit RW 0
3 VDD3_EN2 When 1: RW 0
When SDASR_EN2 is high the supply is on.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 0 the supply
voltage is off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low power mode.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
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