Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Supply voltage (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.0 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 3.3 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 56. VMMC_REG
Address Offset 0x35
Physical Address Instance
Description VMMC regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Supply voltage (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.8 V
SEL[1:0] = 10 : 3.0 V
SEL[1:0] = 11 : 3.3 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 57. VPLL_REG
Address Offset 0x36
Physical Address Instance
Description VPLL regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109