Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013 www.ti.com
Table 49. VDD2_SR_REG (continued)
Type RW
7 6 5 4 3 2 1 0
Reserved SEL
Bits Field Name Description Type Reset
7 Reserved Reserved bit RO 0
R returns
0s
6:0 SEL Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1, RW See
(1)
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35V
...
SEL[6:0] = 0110011: 1.2V
...
SEL[6:0] = 0000001 to 0000011: 0.6V
SEL[6:0] = 0000000: Off (0.0V)
Note: from SEL[6:0] = 3 to 75 (dec)
Vout= (SEL[6:0] × 12.5 mV + 0.5625 V) ×G
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 50. VDD3_REG
Address Offset 0x27
Physical Address Instance
Description VDD2 voltage selection register for smartreflex.
This register can be accessed by both control and smartreflex I
2
C interfaces depending on
SR_CTL_I2C_SEL register bit value.
Type RW
7 6 5 4 3 2 1 0
Reserved CKINEN ST
Bits Field Name Description Type Reset
7:3 Reserved Reserved bit RO 0x00
R returns
0s
2 CKINEN Enable 1Mhz clock synchronization RW 1
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
Table 51. VDIG1_REG
Address Offset 0x30
Physical Address Instance
Description VDIG1 regulator control register
Type RW
7 6 5 4 3 2 1 0
Reserved SEL ST
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