Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013 www.ti.com
7 6 5 4 3 2 1 0
Reserved Reserved ST
VRTC_OFFMASK
Bits Field Name Description Type Reset
7:4 Reserved Reserved bit RO 0x0
R returns
0s
3 VRTC_OFFMASK VRTC internal regulator off mask signal: RW 0
when 1, the regulator keeps its full-load capability during device OFF
state.
when 0, the regulator will enter in low-power mode during device OFF
state.(EEPROM bit)
2 Reserved Reserved bit RO 0
R returns
0s
1:0 ST Reference state: RO 0x1
ST[1:0] = 00 : Reserved
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Reserved
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
Table 43. VIO_REG
Address Offset 0x20
Physical Address Instance
Description VIO control register
Type RW
7 6 5 4 3 2 1 0
ILMAX Reserved SEL ST
Bits Field Name Description Type Reset
7:6 ILMAX Select maximum load current: RW 0x0
when 00: 0.5 A
when 01: 1.0 A
when 10: 1.0 A
when 11: 1.0 A
5:4 Reserved Reserved bit RO 0x0
R returns
0s
3:2 SEL Output voltage selection (EEPROM bits): RW See
(1)
SEL[1:0] = 00 : 1.5 V
SEL[1:0] = 01 : 1.8 V
SEL[1:0] = 10 : 2.5 V
SEL[1:0] = 11 : 3.3 V
1:0 ST Supply state (EEPROM bits): RW 0x0
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109