Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013 www.ti.com
Bits Field Name Description Type Reset
3 IT_ALARM Enable one interrupt when the alarm value is reached (TC ALARM RW 0
registers) by the TC registers
2 IT_TIMER Enable periodic interrupt RW 0
0: interrupt disabled
1: interrupt enabled
1:0 EVERY Interrupt period RW 0x0
00: every second
01: every minute
10: every hour
11: every day
Table 31. RTC_COMP_LSB_REG
Address Offset 0x13
Physical Address Instance
Description RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32kHz oscillator period every hour, micro-controller needs to write FFFF into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type RW
7 6 5 4 3 2 1 0
RTC_COMP_LSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_LSB This register contains the number of 32-kHz periods to be added into the RW 0x00
32-kHz counter every hour [LSB]
Table 32. RTC_COMP_MSB_REG
Address Offset 0x14
Physical Address Instance
Description RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type RW
7 6 5 4 3 2 1 0
RTC_COMP_MSB
Bits Field Name Description Type Reset
7:0 RTC_COMP_MSB This register contains the number of 32-kHz periods to be added into the RW 0x00
32-kHz counter every hour [MSB]
Table 33. RTC_RES_PROG_REG
Address Offset 0x15
Physical Address Instance
Description RTC register containing oscillator resistance value
Type RW
7 6 5 4 3 2 1 0
Reserved SW_RES_PROG
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109