Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Table 29. RTC_STATUS_REG
Address Offset 0x11
Physical Address Instance
Description RTC status register:
NOTES: A dummy read of this register is necessary before each I
2
C read in order to update the status
register value.
Type RW
7 6 5 4 3 2 1 0
POWER_UP ALARM EVENT_1D EVENT_1H EVENT_1M EVENT_1S RUN Reserved
Bits Field Name Description Type Reset
7 POWER_UP Indicates that a reset occurred (bit cleared to 0 by writing 1). RW 1
POWER_UP is set by a reset, is cleared by writing one in this bit.
6 ALARM Indicates that an alarm interrupt has been generated (bit clear by writing RW 0
1).
The alarm interrupt keeps its low level, until the micro-controller write 1 in
the ALARM bit of the RTC_STATUS_REG register.
The timer interrupt is a low-level pulse (15 µs duration).
5 EVENT_1D One day has occurred RO 0
4 EVENT_1H One hour has occurred RO 0
3 EVENT_1M One minute has occurred RO 0
2 EVENT_1S One second has occurred RO 0
1 RUN 0: RTC is frozen RO 0
1: RTC is running
This bit shows the real state of the RTC, indeed because of STOP_RTC
signal was resynchronized on 32-kHz clock, the action of this bit is
delayed.
0 Reserved Reserved bit RO 0
R returns
0s
Table 30. RTC_INTERRUPTS_REG
Address Offset 0x12
Physical Address Instance
Description RTC interrupt control register
Type RW
7 6 5 4 3 2 1 0
Reserved IT_ALARM IT_TIMER EVERY
IT_SLEEP_MASK_EN
Bits Field Name Description Type Reset
7:5 Reserved Reserved bit RO 0x0
R returns
0s
4 IT_SLEEP_MASK_E 1: Mask periodic interrupt while the TPS65910 device is in SLEEP mode. RW 0
N Interrupt event is back up in a register and occurred as soon as the
TPS65910 device is no more in SLEEP mode.
0: Normal mode, no interrupt masked
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109