Datasheet

SWCS046-017
SCLSR_EN2
VDD2/VFB2
VDD1/VFB1
1.2 V
SCLSR_EN1
NRESPWRON
Low-power mode
PFM (pulse skipping) mode
Switch-on sequence
Switch-off sequence
Device on
PWM mode
SW1
t
dOEN
0 V
t
dVDDEN
t
dEN
3.3 V
t
dVDDEN
t
dSOFF2
t
dEN
t
dEN
SWCS046-016
SCLSR_EN1
VDIG1
1.2 V
VPLL
1.8 V
SCLSR_EN2
NRESPWRON
t
dVEN
t
dEN
Switch-on sequence Switch-off sequence
Device on
t
dEN
t
dEN
t
dSOFF2
t
dEN
Low-power mode
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals
Figure 8 andFigure 9 show the power supplies state control through the SCLSR_EN1 and SDASR_EN2 signals
timing characteristics.
NOTE: Register setting: VDIG1_EN1 = 1, VPLL_EN2 = 1, and VPLL_KEEPON = 1
Figure 8. LDO Type Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in
VDD2_SR_REG
Figure 9. VDD1 and VDD2 Supplies State Control Through SCLSR_EN1 and SCLSR_EN2
Table 8. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dEN
: NREPSWON to supply state
change delay, SCLSR_EN1 or 0 ms
SCLSR_EN2 driven
t
dEN
: SCLSR_EN1 or
SCLSR_EN2 edge to supply state 1 × t
CK32k
= 31 µs
change delay
t
dVDDEN
: SCLSR_EN1 or
SCLSR_EN2 edge to VDD1 or 3 × t
CK32k
= 63 µs
VDD2 dc-dc turn on delay
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