Datasheet

SWCS046-018
PWRHOLD
VIO/VFBIO
VAUX1
VDD2/VFB2
VDD1/VFB1
VPLL
VDAC
VAUX2
VMMC
CLK32KOUT
NRESPWRON
t
dSOFF2
t
dSON1
1.8 V
1.8 V
3.3 V
t
dSON2
t
dSON3
1.2 V
1.8 V
1.8 V
t
dSON4
t
dSON5
1.8 V
t
dSON6
t
dSON7
3.3 V
t
dSON8
t
dSOFF1
Switch-off sequence
t : Switch-on sequence
dSONT
TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Figure 2 shows the 00 Boot mode timing characteristics.
Figure 2. Boot Mode: BOOT1 = 0, BOOT0 = 0
Table 3 lists the 00 Boot mode timing characteristics.
Table 3. Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dSON1
PWRHOLD rising edge to VIO, VAUX1 enable delay 66 × t
CK32k
= 2060 µs
t
dSON2
VIO to VDD2 enable delay 64 × t
CK32k
= 2000 µs
t
dSON3
VDD2 to VDD1 enable delay 64 × t
CK32k
= 2000 µs
t
dSON4
VDD1 to VPLL enable delay 64 × t
CK32k
= 2000 µs
t
dSON5
VPLL to VDAC,VAUX2 enable delay 64 × t
CK32k
= 2000 µs
t
dSON6
VDAC to VMMC enable delay 64 × t
CK32k
= 2000 µs
VMMC to CLK32KOUT rising edge delay 64 × t
CK32k
= 2000 µs
t
dSON8
CLK32KOUT to NRESPWRON rising edge delay 64 × t
CK32k
= 2000 µs
t
dSONT
Total switch-on delay 16 ms
PWRHOLD falling edge to NRESPWRON falling edge
t
dSOFF1
2 × t
CK32k
= 62.5 µs
delay
t
dSOFF1B
NRESPWRON falling edge to CLK32KOUT low delay 3 × t
CK32k
= 92 µs
PWRHOLD falling edge to supplies and reference
t
dSOFF2
5 × t
CK32k
= 154 µs
disable delay
Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),
IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),
VMBCH_SEL = 11.
BOOT1 = 0, BOOT0 = 1
Table 4 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 3.
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