Datasheet

TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
VDAC AND VPLL LDO (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
= 2.5 V, I
OUT
= I
OUTmax
, T = 25°C
DC load regulation On mode, I
OUT
= I
OUTmax
to 0 10 mV
DC line regulation On mode, V
IN
= V
INmin
to V
INmax
@ I
OUT
= I
OUTmax
1 mV
On mode, V
IN
= 3.8 V, I
OUT
= 0.1 × I
OUTmax
to 0.9 ×
Transient load regulation 9 mV
I
OUTmax
in 5 µs
And I
OUT
= 0.9 × I
OUTmax
to 0.1 × I
OUTmax
in 5 µs
Transient line regulation On mode, V
IN
= V
INmin
+ 0.5 V to V
INmin
in 30 µs 0.5 mV
And V
IN
= V
INmin
to V
INmin
+ 0.5 V in 30 µs, I
OUT
=
I
OUTmax
/2
Turn-on time I
OUT
= 0, @ V
OUT
= 0.1 V up to V
OUTmin
100 µs
Turn-on inrush current 300 mA
V
IN
= V
INDC
+ 100 mV
pp
tone, V
INDC+
= 3.8 V, I
OUT
=
Ripple rejection
I
OUTmax
/2
f = 217 Hz 70
dB
f = 50 kHz 40
VPLL internal resistance LDO off 535 kΩ
Ground current On mode, I
OUT
= 0 60
On mode, I
OUT
= I
OUTmax
1600
µA
Low-power mode 12
Off mode 1
SWITCH-ON/-OFF SEQUENCES AND TIMING
Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or
through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.
BOOT1 = 0, BOOT0 = 0
Table 2 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 2.
Table 2. Fixed Boot Mode: 00
TPS65910
Register Bit Description
Boot 00
VDD1_OP_REG SEL VDD1 voltage level selection for boot 1.2 V
VDD1_REG VGAIN_SEL VDD1 Gain selection, x1 or x2 x1
EEPROM VDD1 time slot selection 3
DCDCCTRL_REG VDD1_PSKIP VDD1 pulse skip mode enable skip enabled
VDD2_OP_REG/VDD2_SR_REG SEL VDD2 voltage level selection for boot 1.1 V
VDD2_REG VGAIN_SEL VDD2 Gain selection, x1 or x3 x3
EEPROM VDD2 time slot selection 2
DCDCCTRL_REG VDD2_PSKIP VDD2 pulse skip mode enable skip enabled
VIO_REG SEL VIO voltage selection 1.8 V
EEPROM VIO time slot selection 1
DCDCCTRL_REG VIO_PSKIP VIO pulse skip mode enable skip enabled
EEPROM VDD3 time slot OFF
VDIG1_REG SEL LDO voltage selection 1.2 V
EEPROM LDO time slot OFF
VDIG2_REG SEL LDO voltage selection 1.0 V
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109