Datasheet

User's Guide
SLVU582A–December 2011–Revised May 2012
TPS658643 System Evaluation Board
This user’s guide describes the characteristics, operation, and use of the TPS658643EVM-752 evaluation
module (EVM). The TPS658643EVM-752 is a fully assembled and tested platform for evaluating the
performance of the TPS658643 single-chip, power management device. This document includes
schematic diagrams, a printed-circuit board layout, bill of materials, and test data.
Contents
1 Introduction .................................................................................................................. 3
1.1 Features ............................................................................................................. 3
1.2 Applications ......................................................................................................... 3
1.3 Requirements ....................................................................................................... 3
2 Electrical Performance Specifications .................................................................................... 3
3 Schematic .................................................................................................................... 4
4 Connector and Test Point Descriptions .................................................................................. 8
4.1 Headers and Switches ............................................................................................ 8
4.2 Jumpers ............................................................................................................. 9
5 Setup ........................................................................................................................ 10
6 TPS658643EVM Test Data .............................................................................................. 11
6.1 Operation Waveforms ............................................................................................ 11
7 EVM Assembly Drawings and Layout .................................................................................. 16
8 Bill of Materials ............................................................................................................. 20
List of Figures
1 HPA752A Schematic, Sheet 1 ............................................................................................ 4
2 HPA752A Schematic, Sheet 2 ............................................................................................ 5
3 HPA752A Schematic, Sheet 3 ............................................................................................ 6
4 HPA752A Schematic, Sheet 4 ............................................................................................ 7
5 SM0, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div ............................................ 11
6 SM1, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div ............................................ 12
7 SM2, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div ............................................ 12
8 SM0, SM1, SM2, and LDO1 Start-Up .................................................................................. 13
9 LDO1, LDO2, LDO3, and LDO4 Start-Up .............................................................................. 13
10 LDO4, LDO5, and LDO9 Start-Up....................................................................................... 14
11 32-kHz Clock............................................................................................................... 15
12 Top Assembly – Silkscreen .............................................................................................. 16
13 Top Layer................................................................................................................... 16
14 Layer 2 ...................................................................................................................... 17
15 Layer 3 ...................................................................................................................... 17
16 Layer 4 ...................................................................................................................... 18
17 Layer 5 ...................................................................................................................... 18
18 Layer 6 ...................................................................................................................... 19
19 Bottom Layer............................................................................................................... 19
List of Tables
1
SLVU582A–December 2011–Revised May 2012 TPS658643 System Evaluation Board
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