Datasheet
GATE
CONTROL
LOGIC
OSC
PGND1
VIN_SM1
3.3 Hm
OUT
(L1)
+
_
+
_
LSM1
OUTPUT
VOLTAGE
SETTING
PWMCONTROL SECTION
(SHOWNFORSM1,SAMETOPOLOGY FORSM2)
RAMP PEAK-TO-PEAKVOLTAGE
PROPORTIONAL TOVIN_SM1
ERROR AMP WITH “TYPE-3
LIKE” COMPENSATION
V
O(SM1)
C21
10 Fm
C22
10 Fm
L1
SM1
Phase Control in PWM Mode
PFM Mode Operation
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Figure 43. PWM Operation
The integrated power MOSFETs current is monitored at all times and the power MOSFET is turned off if its
internal short-circuit current limit is reached.
The SM1 and SM2 converters operate synchronized to each other when both are in PWM mode, with converter
SM1 as the master. I
2
C control register bits S1S2PHASE in register SM1_SET2 enables delaying the SM2 PWM
clock with respect to SM1 PWM clock, selecting a phase shift from 0 to 270 degrees. The out-of-phase operation
reduces the average current at the input node, enabling use of smaller input filter capacitors when both
converters are connected to the same input supply.
When using the I
2
C interface, the SM1 and SM2 converters can have the automatic power-saving PFM mode
enabled. When the PFM mode is set, the switching frequency is reduced and the internal bias currents are
decreased, optimizing the converter efficiency under light-load conditions.
In PFM mode, the output voltage is monitored by a voltage comparator, which regulates the output voltage to the
programmed value, V
O(SM1)
. If the output voltage is below V
O(SM1)
, the PFM control circuit turns on the power
stage, applying a burst of pulses to increase the output voltage. When the output voltage exceeds the target
regulation voltage, V
O(SM1)
, the power stage is disabled, and the output voltage drops until it is below the
regulation voltage target, when the power stage is enabled again.
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