Datasheet
V(OUT) + V
(LOW_SYS)
ǒ
1 )
R6
R1
Ǔ
:
where R6 and R1 are external resistors, V
(LOW_SYS)
+ 1 V typical
(1)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Table 3. Integrated Supply and Drivers Power-Up Defaults
SUPPLY POWER-UP DEFAULT OTHER BLOCKS POWER-UP DEFAULT
LDO0 OFF, 3.3 V POWER PATH INPUT TO SYSTEM
LDO1 2.85V, ON PWM OFF
LDO2 3.3 V, ON PWM_LED OFF
LDO3 1.25 V, ON GPIO1 INPUT
LDO4 2.75 V, ON GPIO2 INPUT
LD05 2.81 V, ON GPIO3 INPUT
SIM 1.8 V, OFF ADC OFF
RTC_OUT ON, 3.1 V SM3 (WHITE LED) OFF
LDO_PM 3.3 V, ON @ OUT POWERED RGB DRIVER OFF
SM1 ON, 1.24 V INTERRUPT MASK NONE MASKED
SM2 ON, 1.8 V POWER GOOD MASK ALL MASKED
CHARGER ON
After the internal I
2
C register power-up defaults are loaded the power path control logic is enabled, connecting
the external power source to the OUT pin. A status flag (nRAMLOAD) is set to LO in the SOFT_RESET register,
indicating that the I
2
C registers were loaded with the power-up defaults, and the TPS65820 enters the HOTPLUG
mode.
HOTPLUG: In the HOTPLUG state an independent timer, TDGL(HOTPLUG) is started. The hotplug deglitch
timer, when active (not expired), prevents the TPS65820 from entering the SLEEP mode. This functionality
avoids potential system lockup conditions caused by contact bouncing events, when the TPS65820 is initially
powered by a battery pack insertion. After the hotplug deglitch timer is started the TPS65820 enters the ENABLE
mode.
ENABLE: In the ENABLE mode the R ESPWRON output is set to the LO level, the INT pin mode is set to high
impedance and all the power good comparators that monitor the integrated supply outputs are disabled. The
ENABLE mode is used by the TPS65820 to detect when the main system power rail (OUT pin) is powered and
ready to be used on the internal supply power-up. The OUT pin voltage is sensed by an internal low system
voltage comparator which holds the IC in the ENABLE mode until the system power bus voltage (OUT pin) has
reached a minimum operating voltage, defined by the user. The internal comparator senses the system voltage
at pin SYS_IN, and the threshold for the minimum system operating voltage at the OUT pin is set by the external
divider connected from OUT pin to SYS_IN pin. The threshold voltage is calculated as follows:
The minimum system operating voltage should always be set above the internal UVLO threshold V
UVLO
. In
normal application conditions the minimum system operating voltage is usually set to a value that assures that
the TPS65820 integrated regulators are not operating in the dropout region.
When the voltage at the SYS_IN pin exceeds the internal threshold V
(LOW_SYS)
the TPS65820 is ready to start the
system power sequencing, and the SEQUENCING mode is entered.
SEQUENCING – The sequencing state starts immediately after the enable state. In this mode of operation the
integrated supplies are turned ON, according to the sequencing steps loaded from the internal non-volatile
memory during the power-up phase. The TPS65820 sequencing timing diagram shown in figure details the
internal timing delays and supply sequencing. At the end of the sequencing state the user-programmable reset
timer is started, and the TPS65820 enters the reset state.
The startup sequence for the TPS65820 device is controlled by an internal (not user-programmable) EEPROM
configuration byte location that is set at the time of manufacturing. A limited number of variations are possible
according to the configuration table below. The TPS65820 configuration is programmed as 0x02 (or bits 0000
0010). The corresponding startup sequence for the TPS65820 is illustrated in Table 4 ,Table 5 , and Figure 29 .
For alternate startup sequences, a new configuration is required (contact TI factory).
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