Datasheet

SCLK ... ......
SDAT
Slave Address
hA0
Slave Address
hA1
Register
Address
hCMD
....
A6 R0R7R/WA0
0
0
0 0
Start
...
..
D0D7R/WA0A6
1
Slave
Drives
theData
bqDATA
MasterDrives
ACKandStop
RepeatedStart, canbereplacedbya
STOP andSTART
..
SCLK
... ......
SDAT
Slave Address
hA0
HostSends
Data
hDATA
Register
Address
hCMD
.........
A6 R6 R5 R0 D7 D6 D5 D0R7R/WA0A4A5
0 0 0 0
PStart
bqA bqA bqA hA PS
bqA bqA bqA
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Valid Write Sequences
One-Byte Write
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 .............................................................................................................................................................. www.ti.com
The I
2
C write protocol is similar to the read, without the need for a repeated start and bus being set in write
mode. In a WRITE it is not necessary to end each 1 byte WRITE command with a STOP, a START has the
same effect (repeated start).
Figure 25. I
2
C read and write operations
The host can complete a READ or a WRITE sequence with either a STOP or a START.
The TPS65820 always ACKs its own address. If the CMD points to an allowable READ or WRITE address, the
bq writes the address into its RAM address register and sends an ACK. If the CMD points to a non-allowed
address, bq does NOT write the address into its RAM address register, and sends an NACK.
S hA0 bqA
S hA0 bqA hCMD bqA
S hA0 bqA hCMD_N bqN
The data is written to the addressed register when the bq ACK ending the one-byte write sequence is received.
The host can cancel a WRITE by sending a STOP or START before the trailing edge of the bq ACK clock pulse.
S hA0 bqA hCMD bqA hDATA bqA
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