Datasheet

www.ti.com
8 CHANNEL
MUX
CURRENT SAMPLE
ARITHMETICLOGIC
UNIT
ANLG1
ANLG2
T
J
TS
ISET1
RTC_OUT
OUT
BAT
10 BIT SUCCESSIVE
APROXIMATION ADC
SUPPLY REF
ACCUMULATOR
TRIGGERCONTROL
AND
SYNCHRONIZATION
START DONE
ADCREFERENCE
ANDSUPPLY
SELECTION
BIASCONTROL
ANLG 1/
ANLG 2 BIAS
SELECTION
ADCSUPPLY
AND
REFERENCE
SELECTION
OUT
ADC
CHANNEL
SELECTION
ADCCONFIGURATION :
TRIGGER, HOLDOFF, REPEAT
MODES
DELAY ANDWAIT TIMING
ALUMODE :
SINGLE,
AVERAGE ,
MIN,, MAX
TOI2C:
STATUS AND
CONVERSION
DATA
ADC_REF
I2C
I2C
TPS65810
A 2
4.7 Fm
ADC Conversion Cycle
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
4. Arithmetic Logic Unit (ALU): The ALU performs mathematical operations on the ADC output data as
defined by the I
2
C ADC_READING registers. It executes average calculations or minimum /maximum
detection. The result of the calculations is stored in a 11 bit accumulator register (1 bit allocated for
carry-over). The accumulator value is transferred to the I
2
C data register at the end of a conversion cycle.
A simplified block diagram for the ADC is shown in Figure 47 .
Figure 47. ADC Simplified Block Diagram
A conversion cycle includes all the steps required to successfully sample the selected input signal and transfer
the converted data to the I
2
C, generating an interrupt request to the host ( pin: HI → LO). The number of individual
conversions (samples) in a conversion cycle is defined by the I
2
C ADC_SET register bits READ_MODE settings,
and can range from a single sample to 256 samples. The conversion cycle settings for the ALU is defined by
register ADC_READING and it can be set to average, maximum value detection, minimum value detection or no
processing (ADC engine output loaded in the accumulator directly).
The conversion cycle starts with the first sampling and ends when:
• The required ALU operations are performed on the final sample, and
• The ALU accumulator data is transferred to the I
2
C ADC_READING register, and
• The register bit ADC_STATUS in the ADC_READING register is set to LO.
A conversion cycle is always started by the external host when the ADC_EN bit in the ADC_SET register is
toggled from LO to HI by a I
2
C write operation. Resetting the ADC_EN bit to LO before the current conversion
cycle ends ( INT: LO → HI, ADC_STATUS bit set to LO) is not recommended, as the ADC keeps its current
configuration until the current conversion cycle ends.
At the end of a conversion cycle the output data is stored at registers in the ALU block. The ADC_STATUS bit is
set to LO ( DONE ) and an interrupt is generated ( INT pin: HI → LO ) if the ADC_STATUS bit is unmasked, at the
interrupt masking registers INT_MASK. It should be noted that the minimum, maximum and average values are
ALWAYS calculated by the ALU for each conversion cycle.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 69
Product Folder Link(s): TPS65810 TPS65811