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ELECTRICAL CHARACTERISTICS – I
2
C INTERFACE
t
su(STOP)
t
(BUF)
STOP
START
1
9873
2
1
9873
2
ACK
ACK
SCL
SCL
SDA
SDA
t
su(STA)
START
t
r
STOP
t
h(STA)
t
h(DAT)
t
su(DAT)
SCL
SDA
t
w(H)
t
w(L)
t
f
t
r
t
f
t
h(DAT)
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
Over recommended operating conditions (typical values at T
J
= 25 ° C), application circuit as in Figure 3 (unless otherwise
noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
2
C TIMING CHARACTERISTICS
t
R
SCLK/SDATA rise time 300
t
F
SCLK/SDATA fall time 300 ns
t
W(H)
SCLK pulse width high 600
t
W(L)
SCLK Pulse Width Low 1.3 µ s
t
SU(STA)
Setup time for START condition 600
t
H(STA)
START condition hold time after which first clock pulse is generated 600
t
SU(DAT)
Data setup time 100 ns
t
H(DAT)
Data hold time 0
t
SU(STOP)
Setup time for STOP condition 600
t
(BUF)
Bus free time between START and STOP condition 1.3 µ s
FSCL Clock Frequency 400 kHz
I
2
C INTERFACE LOGIC LEVELS
V
IH
High level input voltage 1.3 6
V
V
IL
Low level input voltage 0 0.6
I
H
Input bias current 0.01 µ A
Figure 2. I
2
C Timing
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