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OUT
RESPWRON
INT
RESET DELAY
PROGRAMMEDBY EXTERNAL CAPACITOR
CONNECTED TOPIN TRSTPWON
Power Applied
SEQUENCING
RESET
NOPOWER
I CRegistersLoaded
FromEEPROM
2
ENABLE
HIGHIMPEDANCE HIGHIMPEDANCEHIGHIMPEDANCE
SeeNote2
NORMAL
AC,USBorBAT
V
UVLO
V
UVLO
V
LOW_SYS
SYS_IN
RTC_OUT
LDO1
LDO2
LDO4
LDO5
LDO3
SM2
SeeNote1
SeeNote1
SM1
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
(1) SM1 and SM2 are externally enabled by GPIO1 and GPIO2. This waveform represents the earliest time that SM1 and
SM2 are enabled if GPIO1 and GPIO2 are tied high.
(2) LDO5, SM1, and SM2 are all enabled at the same time. This waveform represents the earliest time that LDO5 is
enabled if VIN_LDO35 is connected to OUT. LDO5 power up can be synchronized to SM1 or SM2 by connecting
VIN_LDO35 to the SM1 or SM2 output, respectively.
Figure 29. TPS65810 Supply Sequencing Timing
RESET – When the reset state starts the RESPWRON output is LO. The user can program the reset timer value
selecting the value of the external capacitor connected to pin TRSTPWON, as shown below:
T
(RESET)
= K
RESET
° C
TRSTPWON
; where K
RESET
is the reset timer constant (1 ms/nF typ)
The TPS65810 RESPWRON pin should be used to reset the external host. During the external host reset
( RESPWRON = LO) the I
2
C SDA and SCL pins are not used to access TPS65810 internal registers. If a
non-standard configuration is used to reset the system the SDA and SCL lines should not be used to
communicate with the TPS65810 until RESPWRON = HI, in order to avoid overwriting the integrated power
supply internal power-up settings during the sequencing mode.
The power good comparators are masked during the reset mode. The reset mode ends when the reset timer
expires, and the TPS65810 goes into the power good check mode.
36 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65810 TPS65811