Datasheet

www.ti.com
FUNCTIONALITY REFERENCE GUIDE – HOST INTERFACE AND SYSTEM SEQUENCING
INTERRUPT
CONTROLLER
INT
SDAT
SCLK
STATEMACHINE
ANDRESET
CONTROLLER
HOT_ RST
RESPWRON
TRSTPWON
SYS_IN
HOST INTERFACE
ANDSEQUENCING
I2CENGINE
OUT
0.1 uF
A 1
2K
10 0K
2K
HOST
TPS 65810
10 0K
A1
A1
R5 R3
R 2
R 4
C
TRSTPWON
210 K
R 6
R 1
100 K
C 16
100 nF
10 0K
V SM2
R7
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
INTERRUPT CONTROLLER, OPEN-DRAIN OUTPUT (INT)
System Parameters Monitored by Interrupt Controller Power up
default
Supply Output System
Charger Status Input and Output
Power Good Fault Status ADC status
Transition Power Transition
Detection
(1)
Modification
Charge: Pre ↔ Fast
SM1, ADC conversion end
Thermal Fault or ↔ Done AC detected: yes ↔ no
SM2, ADC
GPIO 1,2 DPPM:on ↔ off USB detected: yes ↔ no
SM3, Input out of range
configured as Charge Suspend: on ↔ Input OVP: yes ↔ no
All interrupt
LDO1, LDO2, External resistive
external interrupt off System Power: AC ↔
controller
LDO3, LDO4, load connected to
request Thermal Foldback: on USB
inputs set to
LDO5 ANLG1
↔ off
non-masked
Can be masked Individually
Can be masked as a group via a single I
2
C mask
via I
2
C. Blanked during Can be masked Individually via I
2
C
register bit
initial power up
(1) For all supplies (except) for SM3 an output fault is detected if the output voltage is below 90% of the programmed regulation voltage. In
the SM3 converter an output fault indicates that the output OVP threshold was reached.
EVENTS TRIGGERING TPS65810 OPERATING MODE CHANGES
EVENT POWER GOOD FAULT THERMAL HARDWARE SOFTWARE
DETECTION
(1)
FAULT RESET RESET
How transition is Integrated regulator output Internal IC junction Using HOT_RST control I
2
C register control bit
triggered voltage below target value: temperature pin
SM1, SM2, SM3, LDO1,
LDO2,LDO3, LDO4, LDO5
Operating mode Sets Sleep mode or starts a Sets Sleep mode when Generates external host Generates external host
change new power-up cycle when thermal fault is detected reset pulse at pin reset pulse at pin
power good fault is detected RESPWON when RESPWON when I
2
C
(see state machine diagram). HOT_RST=LO. control bit is set.
Power good fault detection Input and Battery power Pulse duration set by Pulse duration set by
comparators are blanked during cycling required to exit external capacitor. external capacitor.
initial power-up. sleep
Controls Can be masked Individually via Fixed Internal Threshold External Input Set via I
2
C
I
2
C.
(1) For all supplies (except) for SM3 an output fault is detected if the output voltage is below 90% of the programmed regulation voltage. In
the SM3 converter an output fault indicates that the output OVP threshold was reached.
Figure 26. Required External Components, Recommended Values, External Connections
32 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS65810 TPS65811