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STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT0
LSB
ACKNOWLEDGE
(hA orbqA)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT 0
LSB
NOT
ACKNOWLEDGE
(hNorbqN)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
SCL
SDA
DATA LINE
STABLE
DATA
CHANGE
ALLOWED
BIT 5-1
I
2
C Read and Write Operations
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
Table 2. I
2
C Naming Conventions Used (continued)
CONDITION CODE
TPS65810 register address sent from TPS65810, bus direction is from TPS65810 to host (READ) hA1
Non-valid I
2
C slave address sent from host hA_N
Valid TPS65810 register address sent from host HCMD
Non-valid TPS65810 register address sent from host HCMD_N
I/O data byte (8 bits) sent from host to TPS65810 hDATA
I/O data byte (8 bits) sent from TPS65810 to host bqDATA
Acknowledge (ACK) from host hA
Not acknowledge (NACK) from host hN
Acknowledge (ACK) from TPS65810 bqA
Not acknowledge (NACK) from TPS65810 bqN
Figure 24. I
2
C operation waveforms
For normal data transfers, SDA is allowed to change only when SCL is low, and one clock pulse is used per bit
of data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high are
reserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition and
terminated with a stop condition.
When addressed, the TPS65810 device generates an acknowledge bit after the reception of each byte by pulling
the SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is associated
with the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65810 leaves the data line high,
enabling a STOP condition generation.
The TPS65810 supports the standard I
2
C one byte Write. The basic I
2
C read protocol has the following steps:
• Host sends a start and sets TPS65810 I
2
C slave address in write mode
• TPS65810 ACK ’ s that this is a valid I
2
C address and that the bus is configured for write
• Host sends TPS65810 register address
• TPS65810 ACK ’ s that this is a valid register and stores the register address to be read
• Host sends a repeated start and TPS65810 I
2
C slave address, reconfiguring the bus for read
• TPS65810 ACK ’ s that this is a valid address and that bus is reconfigured
• Bus is in read mode, TPS65810 starts sending data from selected register
The I
2
C write protocol is similar to the read, without the need for a repeated start and bus being set in write
mode. In a WRITE, it is not necessary to end each 1-byte WRITE command with a STOP; a START has the
same effect (repeated start).
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