Datasheet

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ELECTRICAL CHARACTERISTICS – ADC
V(OUT) * 1.2
500 kW
TPS65810
TPS65811
SLVS658B – MARCH 2006 – REVISED FEBRUARY 2007
Over recommended operating conditions (typical values at T
J
= 25 ° C), V(ADC_REF) =2.535v if external reference voltage is
used, application circuit as in Figure 3 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full scale input range Ch1 to Positive inputs (active clamp) V(ADC_
V
RNG(CH1_5)
0 V
Ch5 Full scale ~ 2.535 V REF)
Full scale input range Ch6 to V
INTREF
V
RNG(CH6_8)
Positive inputs (active clamp), full scale ~4.7 V 0 V
Ch8 × 1.854
Input capacitance (all
C
IN(ADC)
15 pF
channels)
R
INADC(CH1_5)
Input resistance (Ch1 to Ch5) 1 M Ω
I
LKGADC(CH1_5)
Leakage current (Ch1 to Ch5) 100 nA
R
INADC(CH6_8)
Input resistance (Ch6 to Ch8) 430 540 k Ω
I
LKGADC(CH6_8)
Leakage current (Ch6 to Ch8) 10 µ A
T
J
= 25 ° C, ADC channel 5 input voltage 1.895 V
Internal voltage proportional to
V
CH5(ADC)
junction temperature
Temperature coefficient 6.5 mV/ ° C
DC ACCURACY
RES
(ADC)
Resolution SAR ADC 10 Bits
MCD
(ADC)
No missing codes SPECIFIED
INL
(ADC)
Integral linearity error ± 3 LSB
DNL
(ADC)
Differential non-linearity error ± 1 LSB
Difference between the first code transition
OFF
ZERO(ADC)
Offset error 5 LSB
(00...00 to 00...01) and the ideal AGND + 1 LSB
Offset error match between
OFF
CH(ADC)
5 LSB
channels
Deviation in code from the ideal full scale code
GAIN
ADC
Gain error ± 8 LSB
(11 … 111) for the full scale voltage
GAIN
CH(ADC)
Gain error match Any two channels 2 LSB
THROUGHPUT SPEED
ADC
CLK
Sampling clock 600 750 900 kHz
Sampling, conversion and setting Rs ≤ 200 K for
ADC
TCONV
Conversion time 44 59 68 µ s
CH1,CH2,CH3; Rs ≤ 500 Ω for CH6, CH7, CH8
REFERENCE VOLTAGES
Internal ADC reference T
A
= 25 ° C, V(ADC_REF)=V
INTREF
when internal
V
INTREF
2.53 2.535 2.54 V
voltage ADC reference is selected
Internal reference short circuit V(ADC_REF)= AGND1, internal reference
I
SHRT(INTREF)
6 mA
limit enabled via I
2
C
ADC internal reference
V
REF(DRIFT)
50 100 ppm/ ° C
temperature drift
ADC Internal reference Measured at OUT pin (internal reference) or
I
Q(ADC)
40 µ A
quiescent current ADC_REF pin (external reference)
00 0
ADC channel 2 bias current, set via
01 10
I
2
C register ADC_WAIT bits µ A
ANLG2 pin internal pullup
I
(ANLG2)
10 50
(ADC_CH2I_D1_1, ADC_CH2I _D2)
current source
11 60
Total accuracy, relative to selected value – 25% 25%
00 µ A
ADC channel 1 bias current, set via
01 10
I
2
C register ADC_WAIT bits
ANLG1 pin internal pullup
I
(ANLG1)
(BATIDI_D1, BATIDI _D2)
current source
10 50
11 60
Total accuracy 10% 10%
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