Datasheet

TPS65735
www.ti.com SLVSAI6–JUNE 2011
2.3 Thermal Information
TPS65735
THERMAL METRIC RSN UNITS
32 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
38.9
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
26.5
θ
JB
Junction-to-board thermal resistance
(3)
9.8
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
0.3
ψ
JB
Junction-to-board characterization parameter
(5)
9.8
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
3.5
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2.4 Quiescent Current
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
Q(SLEEP)
Power management core quiescent @ 25° C 8.6 10.5 µA
current in sleep mode V
BAT
= 3.6 V
V
VIN
= 0 V
No load on LDO
CHG_EN, BST_EN grounded
BST_FB = 300 mV
Power management core in sleep
mode / device 'off'
I
Q(ACTIVE)
Power management core quiescent @ 25° C 39 53.5 µA
current in active mode V
BAT
= 3.6 V
V
VIN
= 0 V
Boost enabled but not switching,
H-bridge in grounded state
No load on LDO
Power management core in active
mode
2.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY CHARGER POWER PATH
V
UVLO(VIN)
Undervoltage lockout at power path V
VIN
: 0 V → 4 V 3.2 3.3 3.45 V
input, VIN pin
V
HYS-
Hysteresis on UVLO at power path V
VIN
: 4 V → 0 V 200 300 mV
UVLO(VIN)
input, VIN pin
V
IN-DT
Input power detection threshold Input power detected if: (V
VIN
> V
BAT
40 140 mV
+ V
IN-DT
);
V
BAT
= 3.6 V
V
VIN
: 3.5 V → 4 V
V
HYS-INDT
Hysteresis on V
IN-DT
V
BAT
= 3.6 V 20 mV
V
VIN
: 4 V → 3.5 V
Copyright © 2011, Texas Instruments Incorporated POWER MANAGEMENT CORE 9
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