Datasheet

TPS65735
SLVSAI6–JUNE 2011 www.ti.com
3 APPLICATION INFORMATION
3.1 Applications Schematic
Figure 3-1. TPS65735 Applications Schematic
3.2 Reducing System Quiescent Current (I
Q
)
This PMU device has been optimized for low power applications. If an even lower quiescent current is
desired, the following circuit and configuration can be utilized to reduce system off / sleep quiescent
current further. Please note that this will cause a slight efficiency drop to the overall system due to the
addition of the resistance of the FET that has been added. With this circuit, achieving an I
Q
of less than 1
µA is possible. Please refer to the datasheet of the MCU used in the system to determine the system I
Q
that is possible.
26 APPLICATION INFORMATION Copyright © 2011, Texas Instruments Incorporated
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