Datasheet

TPS65735
SLVSAI6–JUNE 2011 www.ti.com
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
LKG(BST_S
Leakage into BST_SW pin BST_EN signal = LOW (Boost 90 nA
W)
(includes leakage into analog disabled)
h-bridge switches) V
BST_SW
= 4.2 V
No load on BST_OUT pin
I
SWLIM(BST)
Boost MOSFET switch current limit 100 150 200 mA
V
DIODE(BST
Voltage across integrated boost BST_EN signal = HIGH 1.0 V
)
diode during normal operation V
BST_SW
= 16.0 V
I
BST_OUT
= - 2 mA
V
REF(BST)
Boost reference voltage on BST_FB 1.17 1.2 1.23 V
pin
V
REFHYS(BS
Boost reference voltage hysteresis 2 2.5 3.2 %
T)
on BST_FB pin
T
ON(BST)
Maximum on time detection 5 6.5 8 µs
threshold
T
OFF(BST)
Minimum off time detection threshold 1.4 1.75 2.1 µs
T
SHUT(BST)
Boost thermal shutdown threshold 105 °C
T
SHUT-
Boost thermal shutdown threshold 20 °C
HYS(BST)
hysteresis
FULL H-BRIDGE ANALOG SWITCHES
I
Q(HSW)
Operating quiescent current for 5 µA
h-bridge switches
R
DSON(HSW
H-bridge switches on resistance 20 40 Ω
)
T
DELAY(HS
H-bridge switch propagation delay, V
HBxy
= 0 V → V
VLDO
100 ns
W-H)
input switched from low to high
state.
T
DELAY(HS
H-bridge switch propagation delay, V
HBxy
= V
VLDO
→ 0 V 100 ns
W-L)
input switched from high to low
state.
POWER MANAGEMENT CORE CONTROLLER
V
IL(PMIC)
Low logic level for logic signals on IO logic level decreasing: 0.4 V
power management core V
SYS
→ 0 V
(BST_EN, CHG_EN, SLEEP, HBR1, I
IN
= 1 mA
HBR2, HBL1, HBL2)
V
IH(PMIC)
High logic level for signals on power IO logic level increasing: 1.2 V
management core 0 V → V
SYS
(BST_EN, CHG_EN, SLEEP, HBR1, I
IN
= 1 mA
HBR2, HBL1, HBL2)
V
GOOD(LDO
Power fault detection threshold V
VLDO
decreasing 1.96 V
)
V
GOOD_HYS
Power fault detection hysteresis V
VLDO
increasing 50 mV
(LDO)
V
BATCOMP
COMP pin voltage (scaled down V
BAT
= 4.2 V 1.85 V
battery voltage) V
VLDO
= 2.2 V
V
BAT
= 2.5 V 1.10
V
V
VLDO
= 2.2 V
V
BAT
= 4.2 V
1.90 V
V
VLDO
= 3.0 V
V
BAT
= 3.3 V 1.50
V
V
VLDO
= 3.0 V
12 POWER MANAGEMENT CORE Copyright © 2011, Texas Instruments Incorporated
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