Datasheet

TPS65720
TPS65721
www.ti.com SLVS979 –OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
V
SYS
= 3.6V, V
DCDC1
= 2.05V, PFM mode, L = 3.3μH, C
OUTDCDC1
= 4.7μF, V
INLDO1
=2.05V, V
LDO1
=1.85V, T
A
= –40°C to 85°C
typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DCDC1 disabled; the discharge function can be disabled as an
R
DIS
Internal discharge resistor at L 300 400 Ω
EEPROM option
THERMAL PROTECTION FOR DCDC1 AND LDO1
T
SD
Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 30 °C
VLDO1 LOW DROPOUT REGULATOR
V
INLDO
Input voltage range for LDO1 1.8 5.6 V
V
LDO1
LDO1 output voltage range 0.8 3.3 V
V
LDO1
LDO1 output voltage Default output voltage for TPS65720 only 1.85 V
V
FB_LDO1
Feedback voltage Externally adjustable version only: TPS65721 0.8 V
I
FB_LDO1
FB pin input current 0.1 μA
I
O
Output current for LDO1 200 mA
I
SC
LDO1 short circuit current limit VLDO1 = GND; VinLDO1=2.05V 350 500 mA
Dropout voltage at LDO1, YFF package I
O
= 200 mA, V
INLDO
= 2.05 V 180 mV
Dropout voltage at LDO1, RSN package I
O
= 200 mA, V
INLDO
= 2.05 V 120 mV
Output voltage accuracy for LDO1 I
O
= 200 mA –1.5% 2.5%
Line regulation for LDO1 V
INLDO1
= V
LDO1
+ 0.5V (min. 1.8V) to 5.6 V (VSYS), I
O
= 50 mA –1% 1%
Load regulation for LDO1 I
O
= 0 mA to 200 mA for LDO1 –1% 2%
PGOOD debounce time Internal PGOOD comparator at VOUTLDO1 is debounced by 80 μs
Internal soft-start when LDO is enabled;
t
Ramp
V
OUT
Ramp time 250 μs
Time to ramp from 5% to 95% of V
OUT
LDO disabled, discharge function per default disabled in
R
DIS
Internal discharge resistor at VLDO1 250 400 Ω
register
BATTERY VOLTAGE COMPARATOR
Battery voltage comparator threshold voltage Depending on Bits <VBAT0>, <VBAT1>; falling voltage –3% 3% V
Battery voltage comparator threshold voltage
Rising voltage 200 mV
hysteresis
POWER PATH
V
UVLO
Undervoltage lockout V
AC
: 0V → 4V 3.2 3.3 3.45 V
V
HYS-UVLO
Hysteresis on UVLO V
AC
: 4V → 0V 200 300 mV
(Input power detected if V
IN
> V
BAT
+ V
IN-DT
) V
BAT
= 3.6V,
V
IN-DT
Input power detection threshold 40 80 140 mV
V
IN
: 3.5V → 4V
V
HYS-INDT
Hysteresis on VIN-DT V
BAT
= 3.6 V, V
IN
: 4V → 3.5V 20 mV
Time measured from V
IN
: 0V → 5V 1μs
t
DGL(PGOOD)
Deglitch time, input power detected status 2 ms
rise-time to PGOOD = LO
V
OVP
Input over-voltage protection threshold V
AC
: 5 V → 7 V 6.4 6.6 6.8 V
V
HYS-OVP
Hysteresis on OVP V
AC
: 11V → 5V 105 mV
t
BLK(OVP)
Input over-voltage blanking time 50 μs
Time measured from V
AC
: 11V → 5V 1μs
t
REC(OVP)
Input over-voltage recovery time 2 ms
fall-time to <CH_PGOOD>=0
I
SYS
= 0.3A, V
AC
= 4.35V, V
BAT
=4.2V; YFF package 170 285 mV
AC pin to SYS pin dropout voltage
V
DO(AC-SYS)
V
AC
– V
SYS
I
SYS
= 0.3A, V
AC
= 4.35V, V
BAT
=4.2V; RSN package 210 325 mV
I
SYS
= 0.2A, V
AC
= 0V, V
BAT
> 3V; YFF package 80 mV
Battery to SYS pin dropout voltage
V
DO(BAT-SYS)
V
BAT
– V
SYS
I
SYS
= 0.2A, V
AC
= 0V, V
BAT
> 3V; RSN package 120 mV
00: V
AC
> V
SYS
+ V
DO(AC-SYS)
, V
BAT
< 3.3V –5% 3.4 5%
V
BAT
+
00: V
AC
> V
SYS
+ V
DO(AC-SYS)
, V
BAT
>/= 3.3V –5% 5%
200mV
SYS pin voltage regulation selectable register
V
SYS(REG)
V
<CHGCONFIG0> Bits <VSYS1>; <VSYS0> 01: V
AC
> V
SYS
+ V
DO(AC-SYS)
–5% 4.4 5%
10: V
AC
> V
SYS
+ V
DO(AC-SYS)
–5% 5.0 5%
11: V
AC
> V
SYS
+ V
DO(AC-SYS)
–5% 5.5 5%
Bit <AC input current1, AC input current0> = 00 90 95 100 mA
I
AC-MAX
Maximum Input Current Register <CHCONFIG0>
Bit < AC input current1, AC input current0> = 01 or 10 450 475 500 mA
Input voltage threshold when input current is Input current is reduced if voltage at AC falls below VAC-LOW
V
AC-LOW
4.35 4.5 4.65 V
reduced to keep the AC voltage above 4.5V
Output voltage threshold when charging current is V
O(REG)
Bit <V_DPPM> = 1 V
reduced –100mV
V
DPM
Register <CHCONFIG2> Bit <V_DPPM> = 0 4.3 V
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