Datasheet
TPS65720
TPS65721
SLVS979 –OCTOBER 2009
www.ti.com
above a certain limit. In TPS6572x, the voltage at the output of the power path (SYS) is regulated to what is
defined with VSYS[1,0] in register CHCONFIG0. When the current needed for the load and for charging the
battery exceeds the input current limit, the voltage at SYS will collapse. The DPPM loop will reduce the charge
current, such that the total current for the load and the charge current equals the input current limit. This is done
as soon as the voltage at SYS drops 100mV below the target voltage.
Second there is input voltage DPPM. For this, the input voltage to the charger/power path at pin AC is sensed to
avoid the voltage from a USB port or dedicated charger to drop below a certain limit. This control loop will reduce
the input current limit for pin AC as soon as the voltage at AC drops below 4.5V (typically). With Bits
ACinputcurrent[1,0] set to 00 or 01, input voltage DPPM is enabled, with ACinputcurrent=10, input voltage DPPM
is disabled.
Layout Considerations
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulators may show poor line and/or load regulation, and additional stability
issues as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and
short traces for the main current paths. The input capacitors should be placed as close as possible to the IC pins
as well as the inductor and output capacitor.
For TPS65721, connect the PGND pin of the device to the PowerPAD™ land of the PCB and connect the analog
ground connection (GND) to the PGND at the PowerPAD™. Keep the common path to the GND pin, which
returns the small signal components, and the high current of the output capacitors as short as possible to avoid
ground noise. The FB line should be connected right to the output capacitor and routed away from noisy
components and traces (for example, the L1 line). See the EVM users guide for details about the layout.
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