Datasheet

TPS65720

TPS65721

SLVS979 –OCTOBER 2009

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IR1 Register Address: 11h (read)

IR1 B7 B6 B5 B4 B3 B2 B1 BO

Bit name and CH_SLEEP CH_RESET CH_IDLE CH_PRECH CH_CC CH_LDO CH_FAULT CH_SUSP

function

Default 0 0 0 0 0 0 0 0

Default value UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R

loaded by:

Set by: Rising edge of Rising edge of Rising edge of Rising edge of Rising edge of Rising edge of Rising edge of Rising edge of

CH_SLEEP CH_RESET CH_IDLE CH_PRECH CH_CC CH_LDO VBAT_FAULT* TH_SUSP

Read/write R R R R R R R R

Bit 7..0 interrupt register:

0 = no interrupt

1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK1

IR2 Register Address: 12h (read)

IR2 B7 B6 B5 B4 B3 B2 B1 BO

Bit name and GPIO3 GPIO2 GPIO1 GPIO0 PGOODZ_ PGOODZ_ PB_STAT

function DCDC1 LDO1

Default 0 0 0 0 0 0 0 0

Default value UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R

loaded by:

Set by: Rising and Rising and Rising and Rising and Rising edge of Rising edge of Rising and

falling edge of falling edge of falling edge of falling edge of PGOODZ_ PGOODZ_ falling edge of

GPIO3 GPIO2 GPIO1 GPIO0 DCDC1 LDO1 PB_ STAT

Read/write R R R R R R R R

Bit 7..4 GPIO interrupt register:

0 = GPIO status did not change

1 = GPIO status changed; cleared when read; interrupt not masked in register IRMASK2

Bit 3..2 power good interrupt register:

0 = no interrupt (power good)

1 = interrupt occurred (output voltage of DCDC converter or LDO too low); cleared when read

Bit 1 PB_STAT interrupt register:

0 = no interrupt

1 = interrupt occurred; cleared when read; interrupt not masked in register IRMASK2

Product Folder Link(s): TPS65720 TPS65721