Datasheet

TPS65720

TPS65721

www.ti.com

SLVS979 –OCTOBER 2009

IRMASK1 Register Address: 0Eh (read/write)

IRMASK1 B7 B6 B5 B4 B3 B2 B1 BO

Bit name and M_CH_ M_CH_ M_CH_IDLE M_CH_PRECH M_CH_ CC M_CH_ LDO M_CH_ FAULT M_CH_

function SLEEP RESET SUSP

Default 1 1 1 1 1 1 1 1

Default value UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R

loaded by:

Read/write R/W R/W R/W R/W R/W R/W R/W R/W

Bit 7..0 charger state interrupt mask register:

0 = Interrupt not masked

1 = Interrupt masked (no interrupt based on the event)

IRMASK2 Register Address: 0Fh (read/write)

IRMASK2 B7 B6 B5 B4 B3 B2 B1 BO

Bit name M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0 M_PGOODZ_ M_PGOODZ_ M_PB_ STAT

and function DCDC1 LDO1

Default 1 1 1 1 1 1 1 1

Default UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R

value

loaded by:

Read/write R/W R/W R/W R/W R/W R/W R/W R

Bit 7..0 charger state interrupt mask register:

0 = Interrupt not masked

1 = Interrupt masked (no interrupt based on the event)

IR0 Register Address: 10h (read only)

IR0 B7 B6 B5 B4 B3 B2 B1 BO

Bit name and TS_HOT TS_COLD OVP TIMER_FAULT CH_ACTIVE CH_PGOOD VBAT_COMP TH_LOOP

function

Default 0 0 0 0 0 0 0 0

Default value UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R UVLO/R

loaded by:

Set by: Rising edge of Rising edge of Rising edge of Rising edge of Rising edge Rising edge Rising edge of Rising edge of

TS_HOT TS_COLD OVP TIMER_FAULT and falling edge and falling edge VBAT_COMP* TH_LOOP

of CH_ACTIVE of CH_PGOOD

Read/write R R R R R R R R

Bit 7..2 interrupt register:

0 = no interrupt

1 = Interrupt occurred (cleared when read); interrupt not masked in register IRMASK0

The VBAT_COMP interrupt is automatically disabled when the battery voltage comparator is disabled by

clearing Bit 1 in register 04h (VBAT_COMP_EN)

Product Folder Link(s): TPS65720 TPS65721