Datasheet
TPS65720
TPS65721
SLVS979 –OCTOBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
V
SYS
= 3.6V, V
DCDC1
= 2.05V, PFM mode, L = 3.3μH, C
OUTDCDC1
= 4.7μF, V
INLDO1
=2.05V, V
LDO1
=1.85V, T
A
= –40°C to 85°C
typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD
High level input voltage for SCLK, SDAT, GPIOx,
V
IH
GPIOs configured as input 1.2 VSYS V
HOLD_DCDC1, HOLD_LDO1, PB_IN
Low level input voltage for SCLK, SDAT, GPIOx,
V
IL
GPIOs configured as input 0 0.4 V
HOLD_DCDC1, HOLD_LDO1, PB_IN
Low level output voltage for SDAT, GPIOx, INT,
V
OL
GPIOs configured as output; Io=1mA; no internal pull-up 0 0.4 V
RESET
GPIO2, GPIO3 configured as current sink; VOL=0.4V ; for
Sink current for GPIO2, GPIO3 –20% 5 20% mA
Tj=0°C to 85°C
I
OL
Sink current for GPIOx GPIOx configured as open drain output ; output = LOW 3 mA
Minimum voltage for proper current regulation from
V
OL
GPIO2 or GPIO3 to GND if programmed as a Io=5mA; current sink turned on 0.4 V
current sink
VLDO1, VLDO1,
V
RESET-falling
Falling edge; Reset is asserted LOW for TPS65720 V
nom-13% nom-7%
LDO1 out of regulation reset voltage
Rising edge; Reset is released HIGH for TPS65720 after VLDO1,
V
RESET-rising
V
T
RESET
nom-4%
Low to high transition of RESET pin, depending on setting of 9 11 13
ms
Bit RESET_DELAY 70 90 110
T
RESET
Reset delay time on pin RESET
HIGH to LOW transition of RESET pin RESET will go low by
HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at 10 μs
V
reset
falling below the threshold
V
THRESHOLD_down
Threshold voltage for reset input Falling voltage; QFN package only –3% 570 3% mV
V
THRESHOLD_hys
Hysteresis on THRESHOLD Rising voltage; QFN package only 30 mV
T
debounce
Debounce time at PB_IN Rising and falling voltage 39 50 60 ms
PB_IN, SDAT, SCLK, GPIOx configured as output, INT,
I
LKG
Input leakage current 0.2 μA
RESET, output high impedance
STEP-DOWN CONVERTER
V
SYS
Input voltage for DCDC1 2.3 5.6 V
V
SYS
falling 2.15 2.2 2.25 V
UVLO Internal undervoltage lockout threshold hysteresis
V
SYS
rising 120 mV
POWER SWITCH
V
SYS
= V
INDCDC1
= 3.6V, YFF package 350 600
R
DS(ON)
High side MOSFET on-resistance mΩ
V
SYS
= V
INDCDC1
= 3.6V, RSN package 400 650
I
LK_HS
High side MOSFET leakage current V
DS
= 5.6V 1 μA
V
INDCDC1/2
= 3.6 V, YFF package 300 500 mΩ
R
DS(ON)
Low side MOSFET on-resistance
V
INDCDC1/2
= 3.6 V, RSN package 350 550 mΩ
I
LK_LS
Low side MOSFET leakage current VDS = 5.6 V 1 μA
2.3 V ≤ V
IN
≤ 5.6 V, TPS65720 425 600 775 mA
Forward current limit high-side and low side
I
LIMF
MOSFET
2.3 V ≤ V
IN
≤ 5.6 V, TPS65721 625 850 1150 mA
V
SYS
> 2.7 V; TPS65720 200
I
o
DC output current mA
V
SYS
> 2.7 V ; TPS65721 400
OSCILLATOR
f
SW
Oscillator Frequency 2.03 2.25 2.48 MHz
OUTPUT
V
OUT
Output Voltage Range 0.6 Vin V
V
FB
Feedback voltage 0.6 V
I
FB
FB pin input current 0.1 μA
V
IN
= 2.3 V to 5.6 V; PFM operation, 0 mA < I
OUT
< I
OUTMAX
1% 3%
DC Output voltage accuracy
(1)
V
OUT
V
IN
= 2.3 V to 5.6 V, PWM operation, 0 mA < I
OUT
< I
OUTMAX
–2% 2%
DC output voltage load regulation PWM operation 0.5 %/A
VDCDC1, VDCDC1,
V
PGOOD-falling
PGOOD threshold at falling output voltage <PGOODZ_DCDC1> is set to 1 V
nom-14% nom-7%
VDCDC1,
V
PGOOD-rising
PGOOD threshold at rising output voltage <PGOODZ_DCDC1> is set to 0 V
nom-5%
t
Start
Start-up time Time from active EN to Start switching 170 μs
t
Ramp
V
OUT
ramp time Time to ramp from 5% to 95% of V
OUT
250 μs
(1) Output voltage specification does not include tolerance of external voltage programming resistors
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