Datasheet

TPS65720
TPS65721
www.ti.com SLVS979 –OCTOBER 2009
MIN MAX UNIT
f
MAX
Clock frequency 400 kHz
t
wH(HIGH)
Clock high time 600 ns
t
wL(LOW)
Clock low time 1300 ns
t
R
DATA and CLK rise time 300 ns
t
F
DATA and CLK fall time 300 ns
t
h(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
t
h(DATA)
Setup time for repeated START condition 600 ns
t
h(DATA)
Data input hold time 0 ns
t
su(DATA)
Data input setup time 100 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
All registers are set to their default value by one of the following events:
• Voltage at the SYS pin is below the undervoltage lockout voltage (UVLO)
• RESET is active; RESET output is pulled LOW and goes high with a 100ms delay
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