Datasheet

PB_IN

HOLD_DCDC1

HOLD_LDO1

VLDO1

PB_IN

(internallyafter

debounce)

HOLD_DCDC1Bit

<DEFDCDC1:B7>

HOLD_LDO1Bit

<LDO_CTRL:B7>

setHIGHbyI2Cwriteto

VDCDC1

setHIGHbyI2Cwriteto

TPS65720

TPS65721

SLVS979 –OCTOBER 2009

www.ti.com

There is a power-hold pin for DCDC1 (HOLD_DCDC1) and one for LDO1 (HOLD_LDO1). When HOLD_DCDC1

is pulled HIGH, DCDC1 is kept enabled after PB_IN was released HIGH. HOLD_LDO1 serves the same function

and keeps LDO1 enabled after PB_IN was released HIGH. After first power-up by pulling PB_IN = LOW or

applying voltage at AC, the HOLD pins HOLD_DCDC1 and HOLD_LDO1 can also be used as enable pins, such

that they turn on LDO1 or DCDC1, respectively when they are pulled HIGH. This function is available as long as

there is a voltage at the battery. After the battery was removed or was discharged, first power-on needs to be

done by pulling PB_IN=LOW.

Disabling the DCDC converter or LDO, forces the device into shutdown, with a shutdown quiescent current as

defined in the electrical characteristics. In this mode, the low and high side MOSFETs are turned-off and the

entire internal control circuitry is switched-off. For proper operation the PB_IN, HOLD_DCDC1, EN_DLO1 pins

must be terminated and must not be left floating.

PB_IN Input

Enables DCDC1 and LDO1 if pulled to GND. Disables DCDC1 and LDO1 if pulled high. There is no internal

pull-up resistor, so a resistor is needed externally to SYS. SYS is preferred over BAT because it is powered by

either AC or BAT (whichever is higher). If BAT is used, the device may not get a valid HIGH signal if the battery

is deeply discharged even when there is voltage at AC.

The input signal is debounced internally by 50ms. When PB_IN is pulled low, the DCDC1 converter and LDO1

will power-up simultaneously. When PB_IN is de-asserted, both converters are turned off. To leave the

converters on, the HOLD_DCDC1 and HOLD_LDO1 pin need to be asserted high. The HOLD register Bit

<CONTROL1:B5> will keep both, DCDC1 and LDO1 enabled if set to 1. For proper operation the PB_IN,

HOLD_DCDC1 and HOLD_LDO1 pins must be terminated and must not be left floating.

Figure 27. PB_IN Timing

HOLD_DCDC1 Input

Actively high hold input for DCDC1. Logically ORÂ´d with the DCDC1 hold Bit <DEFDCDC1:B7>. If the input is

driven HIGH after PB_IN was pulled LOW, the DCDC1 converter stays on after PB_IN was released.

HOLD_LDO1 Input

Actively high hold input for LDO1. Logically ORÂ´d with the LDO1 hold Bit <LDO_CTRL:B7>. If the input is driven

HIGH after PB_IN was pulled LOW, LDO1 stays on after PB_IN was released.

Product Folder Link(s): TPS65720 TPS65721