TPS65253 High Current, Synchronous Step Down Two Buck Switcher Evaluation Module User's Guide Literature Number: SLVU469 June 2011
Copyright © 2011, Texas Instruments Incorporated SLVU469 – June 2011 Submit Documentation Feedback
Contents 1 2 3 4 5 Introduction ........................................................................................................................ 5 Background ........................................................................................................................ 5 Schematic .......................................................................................................................... 5 Placement .............................................................................
www.ti.com List of Figures 1 TPS65253 Schematic ...................................................................................................... 6 2 Part Placement .............................................................................................................. 7 3 Top Layer .................................................................................................................... 7 4 Mid-Layer 1 ............................................................................
1 Introduction This document presents the information required to power the TPS65253 PMIC as well as the support documentation including schematic and bill of materials. 2 Background The TPS65253 PMIC is designed to provide 3.5-A and 2.5-A continuous outputs with an operational range of 4.5 V to 16 V and an externally set switching frequency ranging from 300 kHz to 1.2 MHz. When the PMIC is not fully loaded, buck1 can be loaded to 4 A and buck 2 to 3 A.
Schematic www.ti.com Figure 1.
Placement www.ti.com 4 Placement Figure 2.
Placement www.ti.com Figure 3. Top Layer Figure 4.
Placement www.ti.com Figure 5. Mid-Layer 2 Figure 6.
Bench Test Setup Conditions www.ti.com 5 Bench Test Setup Conditions 5.1 Headers Description and Jumper Placement LOW_P EN2 Vin:4.5V – 16V PGOOD Vout2 Vout1 EN1 Figure 7. Headers Description and Jumper Placement Test points: Black – GND White – Each output, feed-back, power good and VIN. All marking on PCB.
Bench Test Setup Conditions www.ti.com 5.2 Jumpers Table 2. Jumpers 5.3 JUMPER NO. FUNCTION PLACEMENT COMMENT JP6 BUCK1 enable (EN1) For sequencing do not fit jumper. To disable converter fit jumper to GND. Fit according to test requirement JP15 BUCK2 enable (EN2) For sequencing do not fit jumper. To disable converter fit jumper to GND. Fit according to test requirement JP20 LOW_P Low power: Power save mode ON/OFF. If need low power mode test, should connect V3V.
Power-Up Procedure 6 www.ti.com Power-Up Procedure 1. Define which converters are to be enabled or disabled by connecting the correct jumpers accordingly. 2. Apply a DC voltage to jumper J8. Polarity is clearly marked on the silk-screen. 3. Verify that the relevant converters are powered up by the output voltages. The whole start-up process will take less than 100 ms. PGOOD will be asserted high 32 ms after all converter outputs have reached 90% of nominal voltages. 4.
Bill of Materials www.ti.com Table 4. Bill of Materials (continued) FOOTPRINT MANUFACTURER MANUFACTURER PART NO. VENDER PART NO. DESCRIPTION 10 TP8, TP9, TP9a, TP9b, TP11, TP11a, TP11b, TP20, TP23, TP24 TEST POINT 0.042 Keystone Electronics 5002 5002K-ND TEST POINT PC MINI .040" D WHITE 22 5 TP1, TP2, TP3, TP4, TP5 TEST POINT 0.042 Keystone Electronics 5001 5001K-ND TEST POINT PC MINI .040" D BLACK 23 1 U1 QFN28 [RHD] 24 5 C4, C6, C15, C17, C18 4.
Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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