TPS65252 High Current, Synchronous Step Down Two Buck Switcher Evaluation Module User's Guide Literature Number: SLVU438 January 2011
SLVU438 – January 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated
1 2 3 4 5 Introduction ........................................................................................................................ 5 Background ........................................................................................................................ 5 Schematic .......................................................................................................................... 5 Placement ......................................................................................
www.ti.com List of Figures 1 TPS65252 Schematic ...................................................................................................... 6 2 Top Layer .................................................................................................................... 7 3 Layer 1 8 4 Layer 2 8 5 6 7 ....................................................................................................................... ..................................................................
www.ti.com 1 Introduction This document presents the information required to power the TPS65252 PMIC as well as the support documentation including schematic and bill of materials. 2 Background The TPS65252 PMIC is designed to provide 3-A and 2-A continuous outputs with an operational range of 4.5 V to 18 V and a externally set switching frequency ranging from 300 kHz to 2.2 MHz. When the PMIC is not fully loaded, buck1 can be loaded to 3.5 A and buck 2 to 2.5 A.
Schematic www.ti.com Figure 1.
Placement www.ti.com 4 Placement Figure 2.
Placement www.ti.com Figure 3. Layer 1 Figure 4.
Placement www.ti.com Figure 5. Layer 3 Figure 6.
Bench Test Setup Conditions www.ti.com 5 Bench Test Setup Conditions 5.1 Headers Description and Jumper Placement TP LOW P Vin: 4.5 V – 16 V EN 2 TP TP TP TP TP TP TP Vout 2 TP Vout_1 USB_IN TP TP TP USB_OUT EN 1 TP TP TP Figure 7. Headers Description and Jumper Placement Test points: Black – GND White – Each output, feed-back, power good and VIN. All marking on PCB.
Bench Test Setup Conditions www.ti.com 5.2 Jumpers Table 2. Jumpers 5.3 JUMPER NO. FUNCTION PLACEMENT COMMENT JP15 BUCK1 enable (EN1) For sequencing do not fit jumper. To disable converter fit jumper to GND. Fit according to test requirement JP6 BUCK2 enable (EN2) For sequencing do not fit jumper. To disable converter fit jumper to GND. Fit according to test requirement JP20 LOW_P Low power: Power save mode ON/OFF. If need low power mode test, should connect V3V.
Power-Up Procedure 6 www.ti.com Power-Up Procedure 1. Define which converters are to be enabled or disabled by connecting the correct jumpers accordingly. 2. Apply a DC voltage to jumper J8. Polarity is clearly marked on the silk-screen. 3. Verify that the relevant converters are powered up by the output voltages. The whole start-up process will take less than 100 ms. PGOOD will be asserted after 256 ms. 4. Apply loads to the output connectors. 5.
Bill of Materials www.ti.com Table 4. Bill of Materials (continued) ITEM QUANTITY DESIGNATOR VALUE FOOTPRINT MANUFACTURER MANUFACTURER PART NO. VENDER PART NO. DESCRIPTION 20 1 R23 124 kΩ 603 Panasonic-ECG ERJ-3EKF1243V P124KHDKR-ND RES 124 kΩ 1/10 W 1% 0603 SMD 21 14 TP8, TP9, TP9A, TP9B, TP11, TP11A, TP11B, TP20, TP23, TP24, TP25, TP26, TP27, TP28 TEST POINT 0.042 Keystone Electronics 5002 5002K-ND TEST POINT PC MINI .040" D WHITE 22 5 TP1, TP2, TP3, TP4, TP5 TEST POINT 0.
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