Datasheet

TPS65250
www.ti.com SLVSAA3C –JUNE 2010–REVISED OCTOBER 2012
3.3-V and 6.5 LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
• 10 µF for V7V pin 28
• 3.3 µF for V3V pin 29
Choice of Converter for Pump Operation And Sequencing Requirement
Figure 42. Pump and Dump Pins
Although any converter can be used to feed the pump circuit buck 3 is the best option that allows for an easy
layout as the input of the pump circuit (BSTG pin 35) is next to its switching node and allows for a short
connection for a trace associated to a high frequency switching node. Connect a 22-nF capacitor in series with a
10-Ω resistor from the LX3 node to the BSTDG pin.
The storage capacitor charges in two stages:
1. When V
IN
is applied the capacitor charges in a controlled way to a voltage close to V
IN
at a rate of 0.1 ms/µF.
2. Once the capacitor is charged Buck 3 is enabled and its switching node provides the energy to charge the
capacitor to the final storage voltage. Once this voltage is achieved the pump circuit will only provide current
to compensate the self-discharge of the storage capacitor.
Note that it is important that these two charge stages do not overlap. In other words buck 3 must be enabled only
after the first stage of charging is achieved.
Based on these considerations the following sequencing requirement is required:
Table 4. Sequencing
CONVERTER V FUNCTION SEQUENCING SOFT START
1st supply to start, no delay. EN1 tied to
Buck 1 3.3 System, SoC Use 4.7 nF to achieve SS ~0.5 ms.
V3P3.
Simultaneous start with buck 1. EN2 tied Use 3.9 nF to achieve rationometric start-
Buck 2 2.5 MEM, I/O, SoC
to v3P3. up with respect to Buck 1.
Enabled by SoC. Must start after storage
Buck 3 7.5 Line drivers Use 4.7 nF.
capacitor settles t
I
~V
IN
.
If a 2000-µF capacitor is used for storage, Buck 3 must start at least 200 ms after Buck 1 and Buck 3 are
enabled. There are two possible options to cover the sequencing requirement on Buck 3:
• Use a GPIO from the SoC connected To EN3. There will be a delay of hundreds of ms to a few seconds
before the line drivers are enabled. By then the storage capacitor will be charged to ~V
IN
.
• Fit a capacitor at the EN pin. With a delay of 1.67 ms/nF, a 470-nF capacitor will provide a delay of ~784 ms
from the time when Buck 1 and Buck 2 are enabled to the time when Buck 3 is enabled. This will provide
ample time for the storage capacitor to settle at ~V
IN
and also for addition of more storage capacitance if
required.
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