Datasheet

TPS65250
SLVSAA3C –JUNE 2010–REVISED OCTOBER 2012 www.ti.com
Bootstrap Capacitor Selection
A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
Adjustable Current Limiting Resistor Selection
The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The over current
protection threshold can be optimized by changing the trip resistor. Figure 33 governs the threshold of over
current protection for Buck 1. When selecting a resistor, do not exceed the graph limits. In this example, the over
current threshold is 3.2 A. In order to prevent a premature limit trip, the minimum line is used and the resistor is
100 kΩ.
When setting high-side current limit to large current values, ensure that the additional load immediately prior to
an overcurrent condition will not cause the switching node voltage to exceed 20 V. Additionally, ensure during
worst case operation, with all bucks loaded immediately prior to current limit, the maximum virtual junction
temperature of the device does not exceed 125°C.
Bootstrap Capacitors
The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. For the pump circuit use 0.022 nF. A ceramic capacitor with an X7R or X5R grade dielectric is
recommended because of the stable characteristics over temperature and voltage.
Output Voltage and Feedback Resistors Selection
For the example design, 35.7 kΩ was selected for R10. V
OUT
is 3.3 V, V
REF
= 0.8 V. Using Equation 3, R7 is
calculated as 11.5 kΩ. A standard 80.6-kΩ resistor is chose in this design.
Compensation
TPS65250 is a current mode control dc/dc converter. It uses a transconductance error amplifier. A type-II
compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees. The
following equations show the procedure of designing a peak current mode control dc/dc converter.
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 4 to calculate the compensation network’s resistor
value. In this example, the anticipated cross-over frequency (fc) is 65 kHz. The power stage gain ( ) is 10A/V
and the GM amplifier gain (gm
ps
) is 130 µA/V.
2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the
procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C1).
3. An additional pole can be added to attenuate high frequency noise.
In some applications the transient response performance is the primary goal, a type-III compensation circuit
allows the system having one more zero. The additional zero provides extra phase margin and the system can
achieve an extra high crossover frequency. In this example, a 4.7-nF capacitor can be added at the upper leg of
the output divider. C15 and R10 form a zero, which boost the phase margin and lift the gain so that the converter
has a high crossover frequency at 100 kHz.
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