Datasheet

TPS65250
SLVSAA3C –JUNE 2010–REVISED OCTOBER 2012 www.ti.com
TPS65250 continuously monitors the input voltage. Once the input voltage drops below a release voltage of
10.5 V, the circuit tries to transfer charge from storage capacitor to the input capacitor keeping the input voltage
closer to release value for as long as possible. The release voltage should be set lower than the processor dying
gasp detect voltage. This feature greatly reduces the capacitance required to support the dying gasp operation.
The storage and release circuitry is completely on chip except for the charge and storage capacitors. The control
circuit makes sure that the current charging the storage capacitor is limited during power up and the storage
capacitor is fully charged to its target value before the end of reset (PGOOD pin) flag to the processor is
released. The circuit also features a flag signal issued to the host circuit to indicate that the ‘dump’ stage is in
process (GASP pin). This signal can be used to initiate the dying gasp process and reduce the system
complexity. During the release process Buck 3 must stay enabled, but Buck 1 and Buck 2 can be disabled to
maximize the release time.
TPS65250 features a supervisor circuit that monitors Buck 1 and Buck 3 output voltage and generates an
internal power good (PG) signal. The PGOOD pin is asserted once sequencing is done, all PG signals are
reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high.
TPS65250 also features a low power mode enabled by an external signal, which allows for a reduction on the
input power supplied to the system when the host processor is in stand-by (low activity) mode.
TPS65250 is packaged in a small, thermally efficient QFN RHA40 package.
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