Datasheet

TPS65217A, TPS65217B, TPS65217C, TPS65217D

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SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013

SLEW RATE CONTROL REGISTER (DEFSLEW)

Address – 0x11h (Password Protected)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0

FIELD NAME GO GODSBL PFM_EN1 PFM_EN2 PFM_EN3 SLEW[2:0]

READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W

RESET VALUE 0 0 0 0 0 1 1 0

FIELD NAME BIT DEFINITION

(1)

Go bit

0 – no change

1 – Initiates the transition from present state to the output voltage setting currently stored in

DEFDCDCx register

NOTE: Bit is automatically reset at the end of the voltage transition.

Go disable bit

0 – enabled

GODSBL

1 – disabled; DCDCx output voltage changes whenever set-point is updated in DEFDCDCx register

without having to write to the GO bit. SLEW[2:0] setting does apply.

PFM enable bit, DCDC1

PFM_EN1 0 – DCDC converter operates in PWM / PFM mode, depending on load

1 – DCDC converter is forced into fixed frequency PWM mode

PFM enable bit, DCDC2

PFM_EN2 0 – DCDC converter operates in PWM / PFM mode, depending on load

1 – DCDC converter is forced into fixed frequency PWM mode

PFM enable bit, DCDC3

PFM_EN3 0 – DCDC converter operates in PWM / PFM mode, depending on load

1 – DCDC converter is forced into fixed frequency PWM mode

Output slew rate setting

000 – 224 µs/step (0.11 mV/µs at 25 mV per step)

001 – 112 µs/step (0.22 mV/µs at 25 mV per step)

010 – 56 µs/step (0.45 mV/µs at 25 mV per step)

011 – 28 µs/step (0.90 mV/µs at 25 mV per step)

SLEW[2:0]

100 – 14 µs/step (1.80 mV/µs at 25 mV per step)

101 – 7 µs/step (3.60 mV/µs at 25 mV per step)

110 – 3.5 µs/step (7.2 mV/µs at 25 mV per step)

111 – Immediate; Slew rate is only limited by control loop response time

Note: The actual slew rate depends on the voltage step per code. Please refer to DCDC1 and

DCDC2 register for details.

(1) Slew-rate control applies to all three DCDC converters.

Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D