Datasheet

TPS65217A, TPS65217B, TPS65217C, TPS65217D
www.ti.com SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013
POWER GOOD CONTROL REGISTER (DEFPG)
Address – 0x0Dh (Password Protected)
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME not used not used not used not used LDO1PGM LDO2PGM PGDLY[1:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 0 0 1 1 0 0
FIELD NAME BIT DEFINITION
not used N/A
not used N/A
not used N/A
not used N/A
LDO1 power-good masking bit
LDO1PGM 0 – PGOOD pin is pulled low if LDO1_PG is low
1 – LDO1_PG status does not affect the status of the PGOOD output pin
LDO2 power-good masking bit
LDO2PGM 0 – PGOOD pin is pulled low if LDO2_PG is low
1 – LDO2_PG status does not affect the status of the PGOOD output pin
Power Good delay
00 – 20 ms
01 – 100 ms
PGDLY[1:0]
10 – 200 ms
11 – 400 ms
Note: PGDLY applies to PGOOD pin.
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