Datasheet

TPS65217A, TPS65217B, TPS65217C, TPS65217D
www.ti.com SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013
DATA TRANSMISSION TIMING
V
BAT
= 3.6 V ±5%, T
A
= 25ºC, C
L
= 100 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Serial clock frequency 100 400 kHz
Hold time (repeated) START SCL = 100 KHz 4 µs
t
HD;STA
condition. After this period, the first
SCL = 400 KHz 600 ns
clock pulse is generated
SCL = 100 KHz 4.7
t
LOW
LOW period of the SCL clock µs
SCL = 400 KHz 1.3
SCL = 100 KHz 4 µs
t
HIGH
HIGH period of the SCL clock
SCL = 400 KHz 600 ns
SCL = 100 KHz 4.7 µs
Set-up time for a repeated START
t
SU;STA
condition
SCL = 400 KHz 600 ns
SCL = 100 KHz 0 3.45 µs
t
HD;DAT
Data hold time
SCL = 400 KHz 0 900 ns
SCL = 100 KHz 250
t
SU;DAT
Data set-up time ns
SCL = 400 KHz 100
SCL = 100 KHz 1000
Rise time of both SDA and SCL
t
r
ns
signals
SCL = 400 KHz 300
SCL = 100 KHz 300
Fall time of both SDA and SCL
t
f
ns
signals
SCL = 400 KHz 300
SCL = 100 KHz 4 µs
t
SU;STO
Set-up time for STOP condition
SCL = 400 KHz 600 ns
SCL = 100 KHz 4.7
Bus free time between stop and start
t
BUF
µs
condition
SCL = 400 KHz 1.3
SCL = 100 KHz N/A N/A
Pulse width of spikes which mst be
t
SP
suppressed by the input filter
SCL = 400 KHz 0 50 ns
SCL = 100 KHz 400
C
b
Capacitive load for each bus line pF
SCL = 400 KHz 400
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