Datasheet

TPS65217A, TPS65217B, TPS65217C, TPS65217D

SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013

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Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes. The converters need a ceramic input capacitor of 10 µF. The input capacitor can be increased

without any limit for better input voltage filtering. Please refer to Table 2 for recommended ceramic capacitors.

Table 2. Recommended Input Capacitors for DCDC1, 2, and 3

PART NUMBER SUPPLIER VALUE (µF) DIMENSIONS

C2012X5R0J226MT TDK 22 0805

JMK212BJ226MG Taiyo Yuden 22 0805

JMK212BJ106M Taiyo Yuden 10 0805

C2012X5R0J106M TDK 10 0805

STANDBY LDOS (LDO1, LDO2)

LDO1 and LDO2 support up to 100 mA each, are internally current limited and have a maximum drop-out voltage

of 200 mV at rated output current. In SLEEP mode, however, output current is limited to 1 mA each. When

disabled, both outputs are discharged to ground through a 430-Ω resistor.

LDO1 supports an output voltage range of 1.0 V - 1.8 V which is controlled through the DEFLDO1 register. LDO2

supports an output voltage range from 0.9 V - 1.5 V and is controlled through the DEFLDO2 register. By default,

LDO1 is enabled immediately after a power-up event as described in the Modes of Operation section and

remains ON in SLEEP mode to support system standby. Each LDO has low standby-current of < 15 µA typical.

LDO2 can be configured to track the output voltage of DCDC3 (core voltage). When the TRACK bit is set in the

DEFLDO2 register, the output is determined by the DCDC3[5:0] bits of the DEFDCDC3 register and the

LDO2[5:0] bits of the DEFLDO2 register are ignored.

LDO1 and LDO2 can be controlled through STROBE 1-6, special STROBES 14 and 15, or through the

corresponding enable bits in the ENABLE register. By default, LDO1 are controlled through STROBE15 which

keeps it alive in SLEEP mode. The STROBE assignments can be changed by the user while in ACTIVE mode

but be aware that all register settings are reset to default values in SLEEP or OFF mode. This can cause the

LDO to power up automatically when leaving SLEEP mode even tough they have been disabled in SLEEP mode

previously by assigning them to a different strobe or resetting the corresponding enable bit. If this is not desired,

new default values must be programmed into non-volatile memory by the factory. Contact TI for details.

LOAD SWITCHES/LDOS (LS1/LDO3, LS2/LDO4)

TPS65217 provides two general-purpose load switches that can also be configured as LDOs. As LDOs they

support up to 200 mA each, are internally current limited and have a maximum drop-out voltage of 200 mV at

rated output current. LDO3 and LDO4 of the TPS65217C and and TPS65217D devices support up to 400-mA of

current. In either mode ON/OFF state can be controlled either through the sequencer or the LS1_EN and

LS2_EN bits of the ENABLE register. When disabled, both outputs are discharged to ground through a 375-Ω

resistor.

As load switches LS1 and LS2 have a max impedance of 650 mΩ. Different from LDO operation, load switches

can remain in current limit indefinitely without affecting the internal power-good signal or affecting the other rails.

Please note, however, that excessive power dissipation in the switches may cause thermal shutdown of the IC.

Load switch and LDO mode are controlled by LS1LDO3 and LS2LDO4 bits of the DEFLS1 and DEFLS2

registers.

Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D