Datasheet

VDCDC3
L3
10mF
to system
VDCDC3
L3
10mF
to system
)1(
2
1
R
R
VV
REFOUT
+´=
TPS65217A, TPS65217B, TPS65217C, TPS65217D
SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013 www.ti.com
DCDC CONVERTERS
Operation
The TPS65217 step down converters typically operate with 2.25-MHz fixed frequency pulse width modulation
(PWM) at moderate to heavy load currents. At light load currents the converter automatically enters Power Save
Mode and operates in PFM (Pulse Frequency Modulation).
During PWM operation the converter use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle the high-side MOSFET is turned on. The current flows from the
input capacitor via the high-side MOSFET through the inductor to the output capacitor and load. During this
phase, the current ramps up until the PWM comparator trips and the control logic turns off the switch. The
current limit comparator will also turn off the switch in case the current limit of the high-side MOSFET switch is
exceeded. After a dead time preventing shoot through current, the low-side MOSFET rectifier is turned on and
the inductor current ramps down. The current flows now from the inductor to the output capacitor and to the load.
It returns back to the inductor through the low-side MOSFET rectifier.
The next cycle turns off the low-side MOSFET rectifier and turs on the on the high-side MOSFET.
The DC-DC converters operate synchronized to each other, with converter 1 as the master. A 120° phase shift
between DCDC1/DCDC2 and DCDC2/DCDC3 decreases the combined input RMS current at the VIN_DCDCx
pins. Therefore smaller input capacitors can be used.
Output Voltage Setting
The output voltage of the DCDCs can be set in two different ways:
• As a fixed voltage converter where the voltage is defined in register DEFDCDCx.
• An external resistor network. Set the XADJx bit in register DEFDCDCx register and calculate the output
voltage with the following formula:
(1)
Where V
REF
is the feedback voltage of 0.6 V. It is recommended to set the total resistance of R1 + R2 to less
than 1 MΩ. Shield the VDCDC1, VDCDC2, and VDCDC3 lines from switching nodes and inductor L1, L2, and L3
to prevent coupling of noise into the feedback pins.
Figure 14. DCDC1, 2, and 3 Offer Two Methods to Adjust the Output Voltage. Example for DCDC3. LEFT:
fixed voltage options programmable through I
2
C (XADJ3 = 0, default). RIGHT: Voltage is set by external
feedback resistor network (XADJ3 = 1).
Power Save Mode and Pulse Frequency Modulation (PFM)
By default all three DCDC converter enter Pulse Frequency Modulation (PFM) mode at light loads and fixed-
frequency Pulse Width Modulation (PWM) mode at heavy loads. In some applications it is desirable to force
PWM operation even at light loads which can be accomplished by setting the PFM_ENx bits in the DEFSLEW
registers to 0 (default setting is 1). In PFM mode the converter skips switching cycles and operates with reduced
frequency with a minimum quiescent current to maintain high efficiency. The converter will position the output
voltage typically +1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops
caused by a sudden load step.
The transition from PWM to PFM mode occurs once the inductor current in the low-side MOSFET switch
becomes 0.
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Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D