Datasheet

DLY1DLY2DLY3DLY4
STROBE 1
SEQ = 0001
STROBE 2
SEQ = 0010
STROBE 3
SEQ = 0011
STROBE 4
SEQ = 0100
STROBE 5
SEQ = 0101
STROBE15
SEQ = 1111
STROBE14
SEQ = 1110
DLY6
PWR_EN
(input)
DLY5
STROBE 6
SEQ = 0110
DLY6
STROBE 7
SEQ = 0111
DLY5
DLY1DLY2DLY3DLY4DLY5DLY6
PWR_EN
(input)
STROBE 1
SEQ = 0001
STROBE 2
SEQ = 0010
STROBE 3
SEQ = 0011
STROBE 4
SEQ = 0100
STROBE 5
SEQ = 0101
STROBE 6
SEQ = 0110
STROBE 7
SEQ = 0111
TPS65217A, TPS65217B, TPS65217C, TPS65217D
www.ti.com SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013
Figure 3. Power-Down Sequence Follows Reverse Power-Up Sequence. TOP: Power-down sequence
from ON state to OFF state (all rails are turned OFF). BOTTOM: Power-down sequence from ON state to
SLEEP state. STROBE14 and 15 are omitted to allow LDO1/2 to remain ON.
Special Strobes (STROBE 14 and 15)
STROBE 14 and STORBE 15 are not assigned to the main sequencer but used to control rails that are ‘always-
on’, i.e. are powered up as soon as the device exits OFF state and remain ON in SLEEP state. STROBE 14/15
options are available only for LDO1 and LDO2 and not for any of the other rails.
STROBE 14 occurs as soon as the push-button is pressed or the USB or AC adaptor is connected to the device.
After a delay time of DLY6 STROBE 15 occurs. LDO1 and LDO2 can be assigned to either strobe and therefore
can be powered up in any order (contact factory for details - default settings must be factory programmed since
all registers are reset in SLEEP mode).
When a power-down sequence is initiated, STOBE 15 and STOBE 14 will occur only if the OFF bit is set.
Otherwise both strobes are omitted and LDO1 and LDO2 will maintain state.
POWER GOOD
Power-good is a signal used to indicate if an output rail is in regulation or at fault. Internally, all power-good
signals of the enabled rails are monitored at all times and if any of the signals goes low, a fault is declared. All
PGOOD signals are internally deglitched. When a fault occurs, all output rails are powered down and the device
enters OFF state.
The TPS65217 has two PGOOD outputs, one dedicated to LDO1 and 2 (LDO_PGOOD), and one programmable
output (PGOOD). The following rules apply to both outputs:
• The power-up default state for PGOOD/LDO_PGOOD is low. When all rails are disabled, PGOOD and
LDO_PGOOD outputs are both low.
• Only enabled rails are monitored. Disabled rails are ignored.
• Power-good monitoring of a particular rail starts 5ms after the rail has been enabled. It is continuously
monitored thereafter. This allows the rail to power-up.
• PGOOD and LDO_PGOOD outputs are delayed by the PGDLY (20 ms default) after the sequencer is done.
• If an enabled rail goes down due to a fault (output shorted, OTS, UVLO), PGOOD and/or LDO_PGOOD is
declared low, and all rails are shut-down.
• If the user disables a rail (either manually or through sequencer), it has no effect on the PGOOD or
LDO_PGOOD pin.
• If the user disables all rails (either manually or through sequencer) PGOOD and/or LDO_PGOOD will be
pulled low.
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Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D