Datasheet

TPS65217A, TPS65217B, TPS65217C, TPS65217D
SLVSB64F –NOVEMBER 2011–REVISED APRIL 2013 www.ti.com
The power up sequence is executed if one of the following events occurs:
From OFF State:
• Push-button is pressed (falling edge on PB_IN) OR
• USB voltage is asserted (rising edge on USB) OR
• AC adaptor is inserted (rising edge on AC) AND
• PWR_EN pin is asserted (pulled high) AND
• Device is not in Under Voltage Lockout (UVLO) or Over Temperature Shutdown (OTS).
The PWR_EN pin is level sensitive (opposed to edge sensitive) and it makes no difference if it is asserted before
or after the above power-up events. However, it must be asserted within 5 seconds of the power-up event
otherwise the power-down sequence will be triggered and the device enters either OFF state.
From SLEEP State:
• Push-button is pressed (falling edge on PB_IN) OR
• USB voltage is asserted (rising edge on USB) OR
• AC adaptor is inserted (rising edge on AC) AND
• Device is not in Under Voltage Lockout (UVLO) or Over Temperature Shutdown (OTS) OR
• PWR_EN pin is asserted (pulled high).
In SLEEP state the power-up sequence can be triggered by asserting the PWR_EN pin only and the push-button
press or USB/AC assertion are not required.
From ACTIVE State:
The sequencer can be triggered any time by setting the SEQUP bit of the SEQ6 register high. The SEQUP bit is
automatically cleared after the sequencer is done.
Rails that are not assigned to a strobe (SEQ=0000b) are not affected by power-up and power-down sequencing
and will remain in their current ON/OFF state regardless of the sequencer. Any rail can be enabled/disabled at
any time by setting the corresponding enable bit in the ENABLE register with the only exception that the
ENABLE register cannot be accessed while the sequencer is active. Enable bits always reflect the current enable
state of the rail, i.e. the sequencer will set/reset the enable bits for the rails under its control. Also, whenever
faults occur that shut-down the power-rails, the corresponding enable bits will be reset.
Power-Down Sequencing
By default, power-down sequencing follows the reverse power-up sequence. When the power-down sequence is
triggered, STROBE7 occurs first and any rail assigned to STROBE7 will be shut down. After a delay time of
DLY6, STROBE6 occurs and any rail assigned to it will be shut down. The sequence continues until all strobes
have occurred and all DLYx times have been executed.
In some applications it is desired to shut down all rails simultaneously with no delay between rails. Set the
INSTDWN bit in the SEQ6 register to bypass all delay times and shut-down all rails simultaneously when the
power-down sequence is triggered.
A power-down sequence is executed if one of the following events occurs:
• The SEQDWN bit is set.
• The PWR_EN pin is pulled low.
• The push-button is pressed for > 8 s.
• The nRESET pin is pulled low.
• A fault occurs in the IC (OTS, UVLO, PGOOD failure).
• The PWR_EN pin is not asserted (pulled high) within 5 seconds of a power-up event and the OFF bit is set to
1.
When transitioning from ACTIVE to OFF state, any rail not controlled by the sequencer is shut down after the
power-down sequencer has finished. When transitioning from ACTIVE to SLEEP state any rail not controlled by
the power-down sequencer will maintain state. This allows keeping selected power rails up in SLEEP state.
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65217A TPS65217B TPS65217C TPS65217D