Datasheet

TPS65200
www.ti.com SLVSA48 –APRIL 2010
ELECTRICAL CHARACTERISTICS
VBAT = 3.6 V ±5%, T
J
= 27ºC (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
Charger HiZ mode
WLED disabled
2 10
Shunt monitor
disabled
Battery discharge current in high Charger HiZ mode
Impedance mode (CSIN, 0°C < TJ < 85°C, WLED enabled, no
I
DISCHARGE
µA
CSOUT,SWC, SWL, BAT, VSYS V
BAT
= 4.2 V load 1800
pins) Shunt monitor
disabled
Charger HiZ mode
WLED disabled Shunt 60
monitor enabled
Charger PWM ON 10000
V
BUS
> V
BUS(min)
I
VBUS
VBUS supply current Charger PWM OFF 5000 µA
0°C < T
J
< 85°C, HZ_MODE = 1 15
Leakage current from battery to
I
VBUS_LEAK
0°C < T
J
< 85°C, V
BAT
= 4.2 V HiZ mode 5 µA
VBUS pin
VOLTAGE REGULATION
Operating in voltage regulation,
Output charge voltage 3.5 4.44 V
programmable
V
OREG
T
A
= 25°C -0.5 0.5
Voltage regulation accuracy %
Full temperature range -1 1
CURRENT REGULATION -FAST CHARGE
V
SHRT
≤ V
CSOUT
< V
OREG
Output charge current V
BUS
> 5 V, R
SNS
= 20 mΩ, 550 1250
LOW_CHG = 0, Programmable
I
OCHARGE
mA
V
LOWV
≤ V
CSOUT
< V
OREG
,
V
BUS
> 5 V, R
SNS
= 20 mΩ, 150 200
LOW_CHG = 1
CHARGE TERMINATION DETECTION
V
CSOUT
> V
OREG-VRCH
, V
BUS
> 5 V,
I
TERM
Termination charge current 50 400 mA
R
SNS
= 20 mΩ, Programmable
Both rising and falling, 2-mV overdrive,
Deglitch time for charge termination 30 ms
t
RISE
, t
FALL
= 100 ns
CHARGE CURRENT ACCURACY
Offset voltage, sense voltage
amplifier
V
OS, CHRGR
T
A
= 0°C to 85°C -1 1 mV
Charge current accuracy =
V
OS
/(I
SET
xR
SNS
)
BAD ADAPTOR DETECTION
Input voltage lower limit Bad adaptor detection, V
BUS
falling 3.6 3.8 4 V
Deglitch time for V
BUS
rising above Rising voltage, 2-mV over drive,
V
IN(MIN)
30 ms
V
IN(MIN)
t
RISE
= 100 ns
Hysteresis for V
IN(MIN)
V
BUS
rising 100 200 mV
I
ADET
Current source to GND During bad adaptor detection 20 30 40 mA
T
INT
Detection interval Input power source detection 2 s
INPUT BASED DYNAMIC POWER MANAGEMENT
The threshold when input based
Charge mode, programmable 4.2 4.76 V
DPM loop kicks in
V
IN_LOW
DPM loop kick-in threshold
-2 2 %
tolerance
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS65200