Datasheet

TPS65200
www.ti.com SLVSA48 –APRIL 2010
INTERRUPT MASK REGISTER 2 (MASK2)
Address – 0x0Ch
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
CHBATOV
FIELD NAME CHRVPM CHBADM CHTERMM CHRCHGM CH32MM CHTREGM CHDPMM
M
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 0 0 0 0 0 0
FIELD NAME BIT DEFINITION
(1)
Charger reverse protection interrupt mask
CHRVPM 0 – Interrupt not masked
1 – Interrupt masked
Charger Bad adaptor interrupt mask
CHBADM 0 – Interrupt not masked
1 – Interrupt masked
Charger battery overvoltage interrupt mask
CHBATOVM 0 – Interrupt not masked
1 – Interrupt masked
Charge terminated interrupt mask
CHTERMM 0 – Interrupt not masked
1 – Interrupt masked
Charger recharge request interrupt mask
CHRCHGM 0 – Interrupt not masked
1 – Interrupt masked
Charger 32m timeout interrupt mask
CH32MM 0 – Interrupt not masked
1 – Interrupt masked
Charger thermal regulation loop active interrupt mask
CHTREGM 0 – Interrupt not masked
1 – Interrupt masked
Charger input current DPM active interrupt mask
CHDPMM 0 – Interrupt not masked
1 – Interrupt masked
(1) Setting any of the interrupt mask bits does not disable protection circuits. When set, the respective fault will not be signaled on the INT
pin
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